ICH_VMCR Interrupt Controller Virtual Machine Control Register when FEAT_AA32EL2 is implemented, GICv3 is implemented, and (EL2 is implemented or EL3 is implemented) ICH_VMCR_EL2 Architectural AArch64 31 0 31 0 31 0 31 0 Enables the hypervisor to save and restore the virtual machine view of the GIC state. GIC GIC Host Interface Control Registers Virt If EL2 is not implemented, this register is RES0 from EL3. ICH_VMCR is a 32-bit register. VPMR 31 24 31:24 Virtual Priority Mask. The priority mask level for the virtual CPU interface. If the priority of a pending virtual interrupt is higher than the value indicated by this field, the interface signals the virtual interrupt to the PE. This field is an alias of ICV_PMR.Priority. AU VBPR0 23 21 23:21 Virtual Binary Point Register, Group 0. Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field determines Group 0 interrupt preemption, and also determines Group 1 interrupt preemption if ICH_VMCR.VCBPR == 1. This field is an alias of ICV_BPR0.BinaryPoint. AU VBPR1 20 18 20:18 Virtual Binary Point Register, Group 1. Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field determines Group 1 interrupt preemption if ICH_VMCR.VCBPR == 0. This field is an alias of ICV_BPR1.BinaryPoint. AU 17 10 17:10 Reserved, RES0. VEOIM 9 9 9 Virtual EOI mode. Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt: This bit is an alias of ICV_CTLR.EOImode. 0b0 ICV_EOIR0 and ICV_EOIR1 provide both priority drop and interrupt deactivation functionality. Accesses to ICV_DIR are UNPREDICTABLE. 0b1 ICV_EOIR0 and ICV_EOIR1 provide priority drop functionality only. ICV_DIR provides interrupt deactivation functionality. AU 8 5 8:5 Reserved, RES0. VCBPR 4 4 4 Virtual Common Binary Point Register. Possible values of this bit are: This field is an alias of ICV_CTLR.CBPR. 0b0 ICV_BPR0 determines the preemption group for virtual Group 0 interrupts only. ICV_BPR1 determines the preemption group for virtual Group 1 interrupts. 0b1 ICV_BPR0 determines the preemption group for both virtual Group 0 and virtual Group 1 interrupts. Reads of ICV_BPR1 return ICV_BPR0 plus one, saturated to 0b111. Writes to ICV_BPR1 are ignored. AU VFIQEn 3 3 3 Virtual FIQ enable. Possible values of this bit are: This bit is an alias of GICV_CTLR.FIQEn. In implementations where the Non-secure copy of ICC_SRE.SRE is always 1, this bit is RES1. 0b0 Group 0 virtual interrupts are presented as virtual IRQs. 0b1 Group 0 virtual interrupts are presented as virtual FIQs. AU VAckCtl 2 2 2 Virtual AckCtl. Possible values of this bit are: This bit is an alias of GICV_CTLR.AckCtl. This field is supported for backward compatibility with GICv2. Arm deprecates the use of this field. In implementations where the Non-secure copy of ICC_SRE.SRE is always 1, this bit is RES0. 0b0 If the highest priority pending interrupt is Group 1, a read of GICV_IAR or GICV_HPPIR returns an INTID of 1022. 0b1 If the highest priority pending interrupt is Group 1, a read of GICV_IAR or GICV_HPPIR returns the INTID of the corresponding interrupt. AU VENG1 1 1 1 Virtual Group 1 interrupt enable. Possible values of this bit are: This bit is an alias of ICV_IGRPEN1.Enable. 0b0 Virtual Group 1 interrupts are disabled. 0b1 Virtual Group 1 interrupts are enabled. AU VENG0 0 0 0 Virtual Group 0 interrupt enable. Possible values of this bit are: This bit is an alias of ICV_IGRPEN0.Enable. 0b0 Virtual Group 0 interrupts are disabled. 0b1 Virtual Group 0 interrupts are enabled. AU When EL2 is using System register access, EL1 using either System register or memory-mapped access must be supported. MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !(IsFeatureImplemented(FEAT_AA32EL2) && IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then if ICC_HSRE().SRE == '0' then Undefined(); else R(t) = ICH_VMCR(); end; elsif PSTATE.EL == EL3 then if ICC_MSRE().SRE == '0' then Undefined(); else R(t) = ICH_VMCR(); end; end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !(IsFeatureImplemented(FEAT_AA32EL2) && IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then if ICC_HSRE().SRE == '0' then Undefined(); else ICH_VMCR() = R(t); end; elsif PSTATE.EL == EL3 then if ICC_MSRE().SRE == '0' then Undefined(); else ICH_VMCR() = R(t); end; end; 2026-03-26 20:27:25 2026-03_rel