ICH_VTR Interrupt Controller VGIC Type Register when FEAT_AA32EL2 is implemented, GICv3 is implemented, and (EL2 is implemented or EL3 is implemented) ICH_VTR_EL2 Architectural AArch64 31 0 31 0 31 0 31 0 Reports supported GIC virtualization features. GIC GIC Host Interface Control Registers Virt If EL2 is not implemented, all bits in this register are RES0 from EL3, except for nV4, which is RES1 from EL3. ICH_VTR is a 32-bit register. PRIbits 31 29 31:29 Priority bits. The number of virtual priority bits implemented, minus one. An implementation must implement at least 32 levels of virtual priority (5 priority bits). This field is an alias of ICV_CTLR.PRIbits. This field has an IMPLEMENTATION DEFINED value. RO PREbits 28 26 28:26 The number of virtual preemption bits implemented, minus one. An implementation must implement at least 32 levels of virtual preemption priority (5 preemption bits). The value of this field must be less than or equal to the value of ICH_VTR.PRIbits. This field has an IMPLEMENTATION DEFINED value. RO IDbits 25 23 25:23 The number of virtual interrupt identifier bits supported: All other values are reserved. This field is an alias of ICV_CTLR.IDbits. 0b000 16 bits. 0b001 24 bits. RO SEIS 22 22 22 SEI Support. Indicates whether the virtual CPU interface supports generation of SEIs: This bit is an alias of ICV_CTLR.SEIS. 0b0 The virtual CPU interface logic does not support generation of SEIs. 0b1 The virtual CPU interface logic supports generation of SEIs. RO A3V 21 21 21 Affinity 3 Valid. Possible values are: This bit is an alias of ICV_CTLR.A3V. 0b0 The virtual CPU interface logic only supports zero values of Affinity 3 in SGI generation System registers. 0b1 The virtual CPU interface logic supports nonzero values of Affinity 3 in SGI generation System registers. RO nV4 20 20 20 Direct injection of virtual interrupts not supported. Possible values are: In GICv3, the only permitted value is 1. 0b0 The CPU interface logic supports direct injection of virtual interrupts. 0b1 The CPU interface logic does not support direct injection of virtual interrupts. RO TDS 19 19 19 Separate trapping of Non-secure EL1 writes to ICV_DIR supported. FEAT_GICv3_TDIR implements the functionality added by the value 1. 0b0 Implementation does not support ICH_HCR.TDIR. 0b1 Implementation supports ICH_HCR.TDIR. RO 18 5 18:5 Reserved, RES0. ListRegs 4 0 4:0 The number of implemented List registers, minus one. For example, a value of 0b01111 indicates that the maximum of 16 List registers are implemented. This field has an IMPLEMENTATION DEFINED value. RO MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !(IsFeatureImplemented(FEAT_AA32EL2) && IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3))) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then if ICC_HSRE().SRE == '0' then Undefined(); else R(t) = ICH_VTR(); end; elsif PSTATE.EL == EL3 then if ICC_MSRE().SRE == '0' then Undefined(); else R(t) = ICH_VTR(); end; end; 2026-03-26 20:27:25 2026-03_rel