ICV_AP1R<n> Interrupt Controller Virtual Active Priorities Group 1 Registers when FEAT_AA32EL1 is implemented, GICv3 is implemented, and EL2 is implemented 0 3 ICV_AP1R<n>_EL1 Architectural AArch64 31 0 31 0 31 0 31 0 Provides information about virtual Group 1 active priorities. GICV Control GIC ICV_AP1R<n> is a 32-bit register. IMPLEMENTATION DEFINED 31 0 31:0 IMPLEMENTATION DEFINED. 0x00000000 The contents of these registers are IMPLEMENTATION DEFINED with the one architectural requirement that the value 0x00000000 is consistent with no interrupts being active. Writing to these registers with any value other than the last read value of the register (or 0x00000000 when there are no Group 1 active priorities) might result in UNPREDICTABLE behavior of the virtual interrupt prioritization system, causing: Interrupts that should preempt execution to not preempt execution. Interrupts that should not preempt execution to preempt execution. ICV_AP1R1 is implemented only in implementations that support 6 or more bits of priority. ICV_AP1R2 and ICV_AP1R3 are implemented only in implementations that support 7 bits of priority. Unimplemented registers are UNDEFINED. Writing to the active priority registers in any order other than the following order might result in UNPREDICTABLE behavior of the interrupt prioritization system: ICV_AP0R<n>. ICV_AP1R<n>. 0-3 MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} let m:integer = UInt(opc2[1:0]); if !(IsFeatureImplemented(FEAT_AA32EL1) && IsFeatureImplemented(FEAT_GICv3)) then Undefined(); elsif m == 1 && NUM_GIC_PRIORITY_BITS < 6 then Undefined(); elsif (m == 2 || m == 3) && NUM_GIC_PRIORITY_BITS < 7 then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().IRQ == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR().IRQ == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); elsif ICC_SRE().SRE == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && ICH_HCR_EL2().TALL1 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && ICH_HCR().TALL1 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().IMO == '1' then R(t) = ICV_AP1R(m); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().IMO == '1' then R(t) = ICV_AP1R(m); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().IRQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x03); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR().IRQ == '1' then if EL3SDDUndef() then Undefined(); else AArch32_TakeMonitorTrapException(); end; elsif HaveEL(EL3) then R(t) = ICC_AP1R_NS(m); else R(t) = ICC_AP1R(m); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().IRQ == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().IRQ == '1' then Undefined(); elsif ICC_HSRE().SRE == '0' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().IRQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x03); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().IRQ == '1' then if EL3SDDUndef() then Undefined(); else AArch32_TakeMonitorTrapException(); end; elsif HaveEL(EL3) then R(t) = ICC_AP1R_NS(m); else R(t) = ICC_AP1R(m); end; elsif PSTATE.EL == EL3 then if ICC_MSRE().SRE == '0' then Undefined(); else if EffectiveSCR_EL3_NS() == '0' then R(t) = ICC_AP1R_S(m); else R(t) = ICC_AP1R_NS(m); end; end; end; 0-3 MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} let m:integer = UInt(opc2[1:0]); if !(IsFeatureImplemented(FEAT_AA32EL1) && IsFeatureImplemented(FEAT_GICv3)) then Undefined(); elsif m == 1 && NUM_GIC_PRIORITY_BITS < 6 then Undefined(); elsif (m == 2 || m == 3) && NUM_GIC_PRIORITY_BITS < 7 then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().IRQ == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR().IRQ == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); elsif ICC_SRE().SRE == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && ICH_HCR_EL2().TALL1 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && ICH_HCR().TALL1 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().IMO == '1' then ICV_AP1R(m) = R(t); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().IMO == '1' then ICV_AP1R(m) = R(t); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().IRQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x03); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR().IRQ == '1' then if EL3SDDUndef() then Undefined(); else AArch32_TakeMonitorTrapException(); end; elsif HaveEL(EL3) then ICC_AP1R_NS(m) = R(t); else ICC_AP1R(m) = R(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().IRQ == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().IRQ == '1' then Undefined(); elsif ICC_HSRE().SRE == '0' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().IRQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x03); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().IRQ == '1' then if EL3SDDUndef() then Undefined(); else AArch32_TakeMonitorTrapException(); end; elsif HaveEL(EL3) then ICC_AP1R_NS(m) = R(t); else ICC_AP1R(m) = R(t); end; elsif PSTATE.EL == EL3 then if ICC_MSRE().SRE == '0' then Undefined(); else if EffectiveSCR_EL3_NS() == '0' then ICC_AP1R_S(m) = R(t); else ICC_AP1R_NS(m) = R(t); end; end; end; 2026-03-26 20:27:25 2026-03_rel