ID_ISAR1 Instruction Set Attribute Register 1 when FEAT_AA32EL1 is implemented ID_ISAR1_EL1 Architectural AArch64 31 0 31 0 31 0 31 0 Provides information about the instruction sets implemented by the PE in AArch32 state. Must be interpreted with ID_ISAR0, ID_ISAR2, ID_ISAR3, ID_ISAR4, and ID_ISAR5. For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'. Identification Registers ID_ISAR1 is a 32-bit register. Jazelle 31 28 31:28 Indicates the implemented Jazelle extension instructions. All other values are reserved. In Armv8, the only permitted value is 0b0001. 0b0000 No support for Jazelle. 0b0001 Adds the BXJ instruction, and the J bit in the PSR. This setting might indicate a trivial implementation of the Jazelle extension. RO Interwork 27 24 27:24 Indicates the implemented Interworking instructions. All other values are reserved. In Armv8, the only permitted value is 0b0011. 0b0000 None implemented. 0b0001 Adds the BX instruction, and the T bit in the PSR. 0b0010 As for 0b0001, and adds the BLX instruction. PC loads have BX-like behavior. 0b0011 As for 0b0010, and guarantees that data-processing instructions in the A32 instruction set with the PC as the destination and the S bit clear have BX-like behavior. RO Immediate 23 20 23:20 Indicates support for data-processing instructions with long immediates: The MOVT instruction The MOV instruction encodings with zero-extended 16-bit immediates. The T32 ADD and SUB instruction encodings with zero-extended 12-bit immediates, and the other ADD, ADR, and SUB encodings cross-referenced by the pseudocode for those encodings. All other values are reserved. In Armv8, the only permitted value is 0b0001. 0b0000 The specified instructions are not implemented. 0b0001 The specified instructions are implemented. RO IfThen 19 16 19:16 Indicates the implemented If-Then instructions in the T32 instruction set. All other values are reserved. In Armv8, the only permitted value is 0b0001. 0b0000 None implemented. 0b0001 Adds the IT instructions, and the IT bits in the PSRs. RO Extend 15 12 15:12 Indicates the implemented Extend instructions. All other values are reserved. In Armv8, the only permitted value is 0b0010. 0b0000 No scalar sign-extend or zero-extend instructions are implemented, where scalar instructions means non-Advanced SIMD instructions. 0b0001 Adds the SXTB, SXTH, UXTB, and UXTH instructions. 0b0010 As for 0b0001, and adds the SXTB16, SXTAB, SXTAB16, SXTAH, UXTB16, UXTAB, UXTAB16, and UXTAH instructions. RO Except_AR 11 8 11:8 Indicates the implemented A and R-profile exception-handling instructions. All other values are reserved. In Armv8, the only permitted value is 0b0001. 0b0000 None implemented. 0b0001 Adds the SRS and RFE instructions, and the A and R-profile forms of the CPS instruction. RO Except 7 4 7:4 Indicates the implemented exception-handling instructions in the A32 instruction set. All other values are reserved. In Armv8, the only permitted value is 0b0001. 0b0000 Not implemented. This indicates that the User bank and Exception return forms of the LDM and STM instructions are not implemented. 0b0001 Adds the LDM (exception return), LDM (user registers), and STM (user registers) instruction versions. RO Endian 3 0 3:0 Indicates the implemented Endian instructions. All other values are reserved. In Armv8, the permitted values are 0b0000 and 0b0001. 0b0000 None implemented. 0b0001 Adds the SETEND instruction, and the E bit in the PSRs. RO MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T0 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T0 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TID3 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TID3 == '1' then AArch32_TakeHypTrapException(0x03); else R(t) = ID_ISAR1(); end; elsif PSTATE.EL == EL2 then R(t) = ID_ISAR1(); elsif PSTATE.EL == EL3 then R(t) = ID_ISAR1(); end; 2026-03-26 20:27:25 2026-03_rel