ID_ISAR2 Instruction Set Attribute Register 2 when FEAT_AA32EL1 is implemented ID_ISAR2_EL1 Architectural AArch64 31 0 31 0 31 0 31 0 Provides information about the instruction sets implemented by the PE in AArch32 state. Must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR3, ID_ISAR4, and ID_ISAR5. For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'. Identification Registers ID_ISAR2 is a 32-bit register. Reversal 31 28 31:28 Indicates the implemented Reversal instructions. All other values are reserved. In Armv8, the only permitted value is 0b0010. 0b0000 None implemented. 0b0001 Adds the REV, REV16, and REVSH instructions. 0b0010 As for 0b0001, and adds the RBIT instruction. RO PSR_AR 27 24 27:24 Indicates the implemented A and R-profile instructions to manipulate the PSR. All other values are reserved. In Armv8, the only permitted value is 0b0001. The exception return forms of the data-processing instructions are: In the A32 instruction set, data-processing instructions with the PC as the destination and the S bit set. These instructions might be affected by the WithShifts attribute. In the T32 instruction set, the SUBS PC, LR, #N instruction. 0b0000 None implemented. 0b0001 Adds the MRS and MSR instructions, and the exception return forms of data-processing instructions. RO MultU 23 20 23:20 Indicates the implemented advanced unsigned Multiply instructions. All other values are reserved. In Armv8, the only permitted value is 0b0010. 0b0000 None implemented. 0b0001 Adds the UMULL and UMLAL instructions. 0b0010 As for 0b0001, and adds the UMAAL instruction. RO MultS 19 16 19:16 Indicates the implemented advanced signed Multiply instructions. All other values are reserved. In Armv8, the only permitted value is 0b0011. 0b0000 None implemented. 0b0001 Adds the SMULL and SMLAL instructions. 0b0010 As for 0b0001, and adds the SMLABB, SMLABT, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, and SMULWT instructions. Also adds the Q bit in the PSRs. 0b0011 As for 0b0010, and adds the SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, and SMUSDX instructions. RO Mult 15 12 15:12 Indicates the implemented additional Multiply instructions. All other values are reserved. In Armv8, the only permitted value is 0b0010. 0b0000 No additional instructions implemented. This means only MUL is implemented. 0b0001 Adds the MLA instruction. 0b0010 As for 0b0001, and adds the MLS instruction. RO MultiAccessInt 11 8 11:8 Indicates the support for interruptible multi-access instructions. All other values are reserved. In Armv8, the only permitted value is 0b0000. 0b0000 No support. This means the LDM and STM instructions are not interruptible. 0b0001 LDM and STM instructions are restartable. 0b0010 LDM and STM instructions are continuable. RO MemHint 7 4 7:4 Indicates the implemented Memory Hint instructions. All other values are reserved. In Armv8, the only permitted value is 0b0100. 0b0000 None implemented. 0b0001 Adds the PLD instruction. 0b0010 Adds the PLD instruction. (0b0001 and 0b0010 have identical effects.) 0b0011 As for 0b0001 (or 0b0010), and adds the PLI instruction. 0b0100 As for 0b0011, and adds the PLDW instruction. RO LoadStore 3 0 3:0 Indicates the implemented additional load/store instructions. All other values are reserved. In Armv8, the only permitted value is 0b0010. 0b0000 No additional load/store instructions implemented. 0b0001 Adds the LDRD and STRD instructions. 0b0010 As for 0b0001, and adds the Load Acquire (LDAB, LDAH, LDA, LDAEXB, LDAEXH, LDAEX, LDAEXD) and Store Release (STLB, STLH, STL, STLEXB, STLEXH, STLEX, STLEXD) instructions. RO MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T0 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T0 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TID3 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TID3 == '1' then AArch32_TakeHypTrapException(0x03); else R(t) = ID_ISAR2(); end; elsif PSTATE.EL == EL2 then R(t) = ID_ISAR2(); elsif PSTATE.EL == EL3 then R(t) = ID_ISAR2(); end; 2026-03-26 20:27:25 2026-03_rel