ID_ISAR5 Instruction Set Attribute Register 5 when FEAT_AA32EL1 is implemented ID_ISAR5_EL1 Architectural AArch64 31 0 31 0 31 0 31 0 Provides information about the instruction sets implemented by the PE in AArch32 state. Must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR3, and ID_ISAR4. For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'. Identification Registers ID_ISAR5 is a 32-bit register. VCMA 31 28 31:28 Indicates AArch32 support for complex number addition and multiplication where numbers are stored in vectors. All other values are reserved. FEAT_FCMA implements the functionality identified by 0b0001. From Armv8.3, the value 0b0000 is not permitted. 0b0000 The VCMLA and VCADD instructions are not implemented in AArch32. 0b0001 The VCMLA and VCADD instructions are implemented in AArch32. RO RDM 27 24 27:24 Indicates support for the VQRDMLAH and VQRDMLSH instructions in AArch32 state. All other values are reserved. FEAT_RDM implements the functionality identified by the value 0b0001. From Armv8.1, the value 0b0000 is not permitted. 0b0000 No VQRDMLAH and VQRDMLSH instructions implemented. 0b0001 VQRDMLAH and VQRDMLSH instructions implemented. RO 23 20 23:20 Reserved, RES0. CRC32 19 16 19:16 Indicates support for the CRC32 instructions CRC32B, CRC32H, CRC32W, CRC32CB, CRC32CH, and CRC32CW in AArch32 state. All other values are reserved. FEAT_CRC32 implements the functionality identified by the value 0b0001. From Armv8.1, the value 0b0000 is not permitted. 0b0000 CRC32 instructions are not implemented. 0b0001 The specified instructions are implemented. RO SHA2 15 12 15:12 Indicates support for the SHA2 instructions SHA256H, SHA256H2, SHA256SU0, and SHA256SU1 in AArch32 state. All other values are reserved. In Armv8, the permitted values are 0b0000 and 0b0001. 0b0000 No SHA2 instructions implemented. 0b0001 The specified instructions are implemented. RO SHA1 11 8 11:8 Indicates support for the SHA1 instructions SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0, and SHA1SU1 in AArch32 state. All other values are reserved. In Armv8, the permitted values are 0b0000 and 0b0001. 0b0000 No SHA1 instructions implemented. 0b0001 The specified instructions are implemented. RO AES 7 4 7:4 Indicates support for the AES instructions in AArch32 state. All other values are reserved. In Armv8, the permitted values are 0b0000 and 0b0010. 0b0000 No AES instructions implemented. 0b0001 AESE, AESD, AESMC, and AESIMC implemented. 0b0010 As for 0b0001, plus VMULL (polynomial) instructions operating on 64-bit data quantities. RO SEVL 3 0 3:0 Indicates support for the SEVL instruction in AArch32 state. All other values are reserved. In Armv8, the only permitted value is 0b0001. 0b0000 SEVL is implemented as a NOP. 0b0001 SEVL is implemented as Send Event Local. RO MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T0 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T0 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TID3 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TID3 == '1' then AArch32_TakeHypTrapException(0x03); else R(t) = ID_ISAR5(); end; elsif PSTATE.EL == EL2 then R(t) = ID_ISAR5(); elsif PSTATE.EL == EL3 then R(t) = ID_ISAR5(); end; 2026-03-26 20:27:25 2026-03_rel