ID_MMFR2 Memory Model Feature Register 2 when FEAT_AA32EL1 is implemented ID_MMFR2_EL1 Architectural AArch64 31 0 31 0 31 0 31 0 Provides information about the implemented memory model and memory management support in AArch32 state. For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'. Identification Registers ID_MMFR2 is a 32-bit register. HWAccFlg 31 28 31:28 Hardware Access Flag. In earlier versions of the Arm Architecture, this field indicates support for a Hardware Access flag, as part of the VMSAv7 implementation. All other values are reserved. In Armv8, the only permitted value is 0b0000. 0b0000 Not supported. 0b0001 Support for VMSAv7 Access flag, updated in hardware. RO WFIStall 27 24 27:24 Wait For Interrupt Stall. Indicates the support for Wait For Interrupt (WFI) stalling. All other values are reserved. In Armv8, the permitted values are 0b0000 and 0b0001. 0b0000 Not supported. 0b0001 Support for WFI stalling. RO MemBarr 23 20 23:20 Memory Barrier. Indicates the supported memory barrier System instructions in the (coproc == 1111) encoding space. All other values are reserved. In Armv8, the only permitted value is 0b0010. Arm deprecates the use of these operations. ID_ISAR4.Barrier_instrs indicates the level of support for the preferred barrier instructions. 0b0000 None supported. 0b0001 Supported memory barrier System instructions are: Data Synchronization Barrier (DSB). 0b0010 As for 0b0001, and adds: Instruction Synchronization Barrier (ISB). Data Memory Barrier (DMB). RO UniTLB 19 16 19:16 Unified TLB. Indicates the supported TLB maintenance operations, for a unified TLB implementation. All other values are reserved. In Armv8, the only permitted value is 0b0110. 0b0000 Not supported. 0b0001 Supported unified TLB maintenance operations are: Invalidate all entries in the TLB. Invalidate TLB entry by VA. 0b0010 As for 0b0001, and adds: Invalidate TLB entries by ASID match. 0b0011 As for 0b0010, and adds: Invalidate instruction TLB and data TLB entries by VA All ASID. This is a shared unified TLB operation 0b0100 As for 0b0011, and adds: Invalidate Hyp mode unified TLB entry by VA. Invalidate entire Non-secure PL1&0 unified TLB. Invalidate entire Hyp mode unified TLB. 0b0101 As for 0b0100, and adds the following operations: TLBIMVALIS, TLBIMVAALIS, TLBIMVALHIS, TLBIMVAL, TLBIMVAAL, TLBIMVALH. 0b0110 As for 0b0101, and adds the following operations: TLBIIPAS2IS, TLBIIPAS2LIS, TLBIIPAS2, TLBIIPAS2L. RO HvdTLB 15 12 15:12 If the value of ID_MMFR2.UniTLB is not 0b0000, then the meaning of this field is IMPLEMENTATION DEFINED. Arm deprecates the use of this field by software. This field has an IMPLEMENTATION DEFINED value. RO L1HvdRng 11 8 11:8 Level 1 Harvard cache Range. Indicates the supported Level 1 cache maintenance range operations, for a Harvard cache implementation. All other values are reserved. In Armv8, the only permitted value is 0b0000. 0b0000 Not supported. 0b0001 Supported Level 1 Harvard cache maintenance range operations are: Invalidate data cache range by VA. Invalidate instruction cache range by VA. Clean data cache range by VA. Clean and invalidate data cache range by VA. RO L1HvdBG 7 4 7:4 Level 1 Harvard cache Background fetch. Indicates the supported Level 1 cache background fetch operations, for a Harvard cache implementation. When supported, background fetch operations are non-blocking operations. All other values are reserved. In Armv8, the only permitted value is 0b0000. 0b0000 Not supported. 0b0001 Supported Level 1 Harvard cache background fetch operations are: Fetch instruction cache range by VA. Fetch data cache range by VA. RO L1HvdFG 3 0 3:0 Level 1 Harvard cache Foreground fetch. Indicates the supported Level 1 cache foreground fetch operations, for a Harvard cache implementation. When supported, foreground fetch operations are blocking operations. All other values are reserved. In Armv8, the only permitted value is 0b0000. 0b0000 Not supported. 0b0001 Supported Level 1 Harvard cache foreground fetch operations are: Fetch instruction cache range by VA. Fetch data cache range by VA. RO MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T0 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T0 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TID3 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TID3 == '1' then AArch32_TakeHypTrapException(0x03); else R(t) = ID_MMFR2(); end; elsif PSTATE.EL == EL2 then R(t) = ID_MMFR2(); elsif PSTATE.EL == EL3 then R(t) = ID_MMFR2(); end; 2026-03-26 20:27:25 2026-03_rel