ID_MMFR3 Memory Model Feature Register 3 when FEAT_AA32EL1 is implemented ID_MMFR3_EL1 Architectural AArch64 31 0 31 0 31 0 31 0 Provides information about the implemented memory model and memory management support in AArch32 state. For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'. Identification Registers ID_MMFR3 is a 32-bit register. Supersec 31 28 31:28 Supersections. On a VMSA implementation, indicates whether Supersections are supported. All other values are reserved. In Armv8, the permitted values are 0b0000 and 0b1111. 0b0000 Supersections supported. 0b1111 Supersections not supported. RO CMemSz 27 24 27:24 Cached Memory Size. Indicates the physical memory size supported by the caches. All other values are reserved. In Armv8, the permitted values are 0b0000, 0b0001, and 0b0010. 0b0000 4GB, corresponding to a 32-bit physical address range. 0b0001 64GB, corresponding to a 36-bit physical address range. 0b0010 1TB or more, corresponding to a 40-bit or larger physical address range. RO CohWalk 23 20 23:20 Coherent Walk. Indicates whether Translation table updates require a clean to the Point of Unification. All other values are reserved. In Armv8, the only permitted value is 0b0001. 0b0000 Updates to the translation tables require a clean to the Point of Unification to ensure visibility by subsequent translation table walks. 0b0001 Updates to the translation tables do not require a clean to the Point of Unification to ensure visibility by subsequent translation table walks. RO PAN 19 16 19:16 Privileged Access Never. Indicates support for the PAN bit in CPSR, SPSR, and DSPSR in AArch32 state. All other values are reserved. FEAT_PAN implements the functionality identified by the value 0b0001. FEAT_PAN2 implements the functionality added by the value 0b0010. From Armv8.1, the value 0b0000 is not permitted. From Armv8.2, the value 0b0001 is not permitted. 0b0000 PAN not supported. 0b0001 PAN supported. 0b0010 PAN supported and ATS1CPRP and ATS1CPWP instructions supported. RO MaintBcst 15 12 15:12 Maintenance Broadcast. Indicates whether Cache, TLB, and branch predictor operations are broadcast. All other values are reserved. In Armv8, the only permitted value is 0b0010. 0b0000 Cache, TLB, and branch predictor operations only affect local structures. 0b0001 Cache and branch predictor operations affect structures according to shareability and defined behavior of instructions. TLB operations only affect local structures. 0b0010 Cache, TLB, and branch predictor operations affect structures according to shareability and defined behavior of instructions. RO BPMaint 11 8 11:8 Branch Predictor Maintenance. Indicates the supported branch predictor maintenance operations in an implementation with hierarchical cache maintenance operations. All other values are reserved. In Armv8, the only permitted value is 0b0010. 0b0000 None supported. 0b0001 Supported branch predictor maintenance operations are: Invalidate all branch predictors. 0b0010 As for 0b0001, and adds: Invalidate branch predictors by VA. RO CMaintSW 7 4 7:4 Cache Maintenance by Set/Way. Indicates the supported cache maintenance operations by set/way, in an implementation with hierarchical caches. All other values are reserved. In Armv8, the only permitted value is 0b0001. In a unified cache implementation, the data cache maintenance operations apply to the unified caches. 0b0000 None supported. 0b0001 Supported hierarchical cache maintenance instructions by set/way are: Invalidate data cache by set/way. Clean data cache by set/way. Clean and invalidate data cache by set/way. RO CMaintVA 3 0 3:0 Cache Maintenance by Virtual Address. Indicates the supported cache maintenance operations by VA, in an implementation with hierarchical caches. All other values are reserved. In Armv8, the only permitted value is 0b0001. In a unified cache implementation, data cache maintenance operations apply to the unified caches, and the instruction cache maintenance instructions are not implemented. 0b0000 None supported. 0b0001 Supported hierarchical cache maintenance operations by VA are: Invalidate data cache by VA. Clean data cache by VA. Clean and invalidate data cache by VA. Invalidate instruction cache by VA. Invalidate all instruction cache entries. RO MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T0 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T0 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TID3 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TID3 == '1' then AArch32_TakeHypTrapException(0x03); else R(t) = ID_MMFR3(); end; elsif PSTATE.EL == EL2 then R(t) = ID_MMFR3(); elsif PSTATE.EL == EL3 then R(t) = ID_MMFR3(); end; 2026-03-26 20:27:25 2026-03_rel