ID_MMFR4 Memory Model Feature Register 4 when FEAT_AA32EL1 is implemented ID_MMFR4_EL1 Architectural AArch64 31 0 31 0 31 0 31 0 Provides information about the implemented memory model and memory management support in AArch32 state. For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'. Identification Registers ID_MMFR4 is a 32-bit register. EVT 31 28 31:28 Enhanced Virtualization Traps. If EL2 is implemented, indicates support for the HCR2.{TTLBIS, TOCU, TICAB, TID4} traps. All other values are reserved. FEAT_EVT implements the functionality identified by the value 0b0001. FEAT_EVT2 implements the functionality identified by the value 0b0010. If EL2 is not implemented or does not support AArch32, the only permitted value is 0b0000. From Armv8.5, if EL2 is implemented and supports AArch32, the value 0b0001 is not permitted. 0b0000 HCR2.{TTLBIS, TOCU, TICAB, TID4} traps are not supported. 0b0001 HCR2.{TOCU, TICAB, TID4} traps are supported. 0b0010 As 0b0001, and HCR2.TTLBIS trap is supported. RO CCIDX 27 24 27:24 Support for use of the revised CCSIDR format and the presence of the CCSIDR2 is indicated. All other values are reserved. FEAT_CCIDX implements the functionality identified by 0b0001. From Armv8.3, the permitted values are 0b0000 and 0b0001. 0b0000 32-bit format implemented for all levels of the CCSIDR, and the CCSIDR2 register is not implemented. 0b0001 64-bit format implemented for all levels of the CCSIDR, and the CCSIDR2 register is implemented. RO LSM 23 20 23:20 Indicates support for LSMAOE and nTLSMD bits in HSCTLR and SCTLR. All other values are reserved. FEAT_LSMAOC implements the functionality identified by the value 0b0001. From Armv8.2, the permitted values are 0b0000 and 0b0001. 0b0000 LSMAOE and nTLSMD bits not supported. 0b0001 LSMAOE and nTLSMD bits supported. RO HPDS 19 16 19:16 Hierarchical permission disables bits in translation tables. All other values are reserved. FEAT_AA32HPD implements the functionality identified by the value 0b0001. FEAT_HPDS2 implements the functionality added by the value 0b0010. The value 0b0000 implies that the encoding for TTBCR2 is UNDEFINED. 0b0000 Disabling of hierarchical controls not supported. 0b0001 Supports disabling of hierarchical controls using the TTBCR2.HPD0, TTBCR2.HPD1, and HTCR.HPD bits. 0b0010 As for value 0b0001, and adds possible hardware allocation of bits[62:59] of the Translation table descriptors from the final lookup level for IMPLEMENTATION DEFINED use. RO CnP 15 12 15:12 Common not Private translations. All other values are reserved. FEAT_TTCNP implements the functionality identified by the value 0b0001. From Armv8.2, the value 0b0000 is not permitted. 0b0000 Common not Private translations not supported. 0b0001 Common not Private translations supported. RO XNX 11 8 11:8 Support for execute-never control distinction by Exception level at stage 2. All other values are reserved. FEAT_XNX implements the functionality identified by the value 0b0001. When FEAT_XNX is implemented: If all of the following conditions are true, it is IMPLEMENTATION DEFINED whether the value of ID_MMFR4.XNX is 0b0000 or 0b0001: ID_AA64MMFR1_EL1.XNX ==1. EL2 cannot use AArch32. EL1 can use AArch32. If EL2 can use AArch32 then the value 0b0000 is not permitted. 0b0000 Distinction between EL0 and EL1 execute-never control at stage 2 not supported. 0b0001 Distinction between EL0 and EL1 execute-never control at stage 2 supported. RO AC2 7 4 7:4 Indicates the extension of the ACTLR and HACTLR registers using ACTLR2 and HACTLR2. All other values are reserved. In Armv8.0, the permitted values are 0b0000 and 0b0001. From Armv8.2, the only permitted value is 0b0001. 0b0000 ACTLR2 and HACTLR2 are not implemented. 0b0001 ACTLR2 and HACTLR2 are implemented. RO SpecSEI 3 0 3:0 Describes whether the PE can generate SError exceptions from speculative reads of memory, including speculative instruction fetches. All other values are reserved. FEAT_SpecSEI implements the functionality identified by the value 0b0001. 0b0000 The PE never generates an SError exception due to an External abort on a speculative read. 0b0001 The PE might generate an SError exception due to an External abort on a speculative read. RO When FEAT_RAS is implemented 3 0 3:0 Reserved, RES0. Otherwise MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T0 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T0 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && (IsFeatureImplemented(FEAT_FGT) || !IsZero(ID_MMFR4()) || ImpDefBool("ID_MMFR4 trapped by HCR_EL2.TID3")) && HCR_EL2().TID3 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && (IsFeatureImplemented(FEAT_FGT) || !IsZero(ID_MMFR4()) || ImpDefBool("ID_MMFR4 trapped by HCR.TID3")) && HCR().TID3 == '1' then AArch32_TakeHypTrapException(0x03); else R(t) = ID_MMFR4(); end; elsif PSTATE.EL == EL2 then R(t) = ID_MMFR4(); elsif PSTATE.EL == EL3 then R(t) = ID_MMFR4(); end; 2026-03-26 20:27:25 2026-03_rel