ID_PFR0 Processor Feature Register 0 when FEAT_AA32EL1 is implemented ID_PFR0_EL1 Architectural AArch64 31 0 31 0 31 0 31 0 Gives top-level information about the instruction sets and other features supported by the PE in AArch32 state. Must be interpreted with ID_PFR1. For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'. Identification Registers ID_PFR0 is a 32-bit register. RAS 31 28 31:28 RAS Extension version. All other values are reserved. FEAT_RAS implements the functionality identified by the value 0b0001. FEAT_DoubleFault implements the functionality identified by the value 0b0010. When ERRIDR.NUM is zero: If FEAT_DoubleFault is not implemented, then this field is permitted to have the value 0b0001, regardless of whether FEAT_RASv1p1 or FEAT_RASv2 are implemented. If FEAT_DoubleFault is implemented, then this field is permitted to have the value 0b0010, regardless of whether FEAT_RASv2 is implemented. When ERRIDR.NUM is nonzero: FEAT_RASv1p1 implements the functionality identified by the value 0b0010. FEAT_RASv2 implements the functionality identified by the value 0b0011. From Armv8.2, the value 0b0000 is not permitted. From Armv8.4, if FEAT_DoubleFault is implemented or ERRIDR.NUM is nonzero, the value 0b0001 is not permitted. When the value of this field is 0b0001, ID_PFR2.RAS_frac indicates whether FEAT_RASv1p1 is implemented.From Armv8.9, if ERRIDR.NUM is nonzero, the value 0b0010 is not permitted. 0b0000 The RAS Extension is not implemented. 0b0001 The RAS Extension is implemented, FEAT_RAS provides the ESB instruction and the Error synchronization event. 0b0010 FEAT_RASv1p1 implemented. As 0b0001, and adds support for additional ERXMISC<m> System registers. Error records accessed through System registers conform to RAS System Architecture v1.1, which includes simplifications to ERR<n>STATUS and support for the optional RAS Timestamp Extension. 0b0011 FEAT_RASv2 implemented. As 0b0010, and requires that error records accessed through System registers conform to either RAS System Architecture v1.1 or RAS System Architecture v2. RO DIT 27 24 27:24 Data Independent Timing. All other values are reserved. FEAT_DIT implements the functionality identified by the value 0b0001. From Armv8.4, the value 0b0000 is not permitted. 0b0000 AArch32 does not guarantee constant execution time of any instructions. 0b0001 AArch32 provides the PSTATE.DIT mechanism to guarantee constant execution time of certain instructions. RO AMU 23 20 23:20 Indicates support for Activity Monitors Extension. All other values are reserved. FEAT_AMUv1 implements the functionality identified by the value 0b0001. FEAT_AMUv1p1 implements the functionality identified by the value 0b0010. In Armv8.0, the only permitted value is 0b0000. In Armv8.4, the permitted values are 0b0000 and 0b0001. From Armv8.6, the permitted values are 0b0000, 0b0001, and 0b0010. 0b0000 Activity Monitors Extension is not implemented. 0b0001 FEAT_AMUv1 is implemented. 0b0010 FEAT_AMUv1p1 is implemented. As 0b0001 and adds support for virtualization of the activity monitor event counters. RO CSV2 19 16 19:16 Speculative use of out of context branch targets. All other values are reserved. FEAT_CSV2 implements the functionality identified by the value 0b0001. FEAT_CSV2_1p1 implements the functionality identified by the value 0b0010. From Armv8.5, the permitted values are 0b0001 and 0b0010. 0b0000 The implementation does not disclose whether FEAT_CSV2 is implemented. 0b0001 FEAT_CSV2 is implemented, but FEAT_CSV2_1p1 is not implemented. 0b0010 FEAT_CSV2_1p1 is implemented. RO State3 15 12 15:12 T32EE instruction set support. All other values are reserved. In Armv8, the only permitted value is 0b0000. 0b0000 Not implemented. 0b0001 T32EE instruction set implemented. RO State2 11 8 11:8 Jazelle extension support. All other values are reserved. In Armv8, the only permitted value is 0b0001. 0b0000 Not implemented. 0b0001 Jazelle extension implemented, without clearing of JOSCR.CV on exception entry. 0b0010 Jazelle extension implemented, with clearing of JOSCR.CV on exception entry. RO State1 7 4 7:4 T32 instruction set support. All other values are reserved. In Armv8, the only permitted value is 0b0011. 0b0000 T32 instruction set not implemented. 0b0001 T32 encodings before the introduction of Thumb-2 technology implemented: All instructions are 16-bit. A BL or BLX is a pair of 16-bit instructions. 32-bit instructions other than BL and BLX cannot be encoded. 0b0011 T32 encodings after the introduction of Thumb-2 technology implemented, for all 16-bit and 32-bit T32 basic instructions. RO State0 3 0 3:0 A32 instruction set support. All other values are reserved. In Armv8, the only permitted value is 0b0001. 0b0000 A32 instruction set not implemented. 0b0001 A32 instruction set implemented. RO MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T0 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T0 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TID3 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TID3 == '1' then AArch32_TakeHypTrapException(0x03); else R(t) = ID_PFR0(); end; elsif PSTATE.EL == EL2 then R(t) = ID_PFR0(); elsif PSTATE.EL == EL3 then R(t) = ID_PFR0(); end; 2026-03-26 20:27:25 2026-03_rel