ISR Interrupt Status Register when FEAT_AA32EL1 is implemented ISR_EL1 Architectural AArch64 31 0 31 0 31 0 31 0 Shows the pending status of the IRQ and FIQ interrupts and the SError exceptions. Exception ISR is a 32-bit register. 31 9 31:9 Reserved, RES0. A 8 8 8 SError exception pending bit: If all of the following apply then this field shows the pending status of virtual SError exceptions: EL2 is implemented and enabled in the current Security state. Any of the following apply: EL2 is using AArch64 and HCR_EL2.AMO is 1. EL2 is using AArch64, FEAT_DoubleFault2 is implemented, and the Effective value of HCRX_EL2.TMEA is 1. EL2 is using AArch32 and HCR.AMO is 1. The PE is executing at EL1. Otherwise, this field shows the pending status of physical SError exceptions. If the SError exception is edge-triggered, this field is cleared to zero when the physical SError exception is taken. 0b0 No pending SError exception. 0b1 An SError exception is pending. I 7 7 7 IRQ pending bit. Indicates whether an IRQ interrupt is pending: If all of the following apply then this field shows the pending status of virtual IRQ interrupts: EL2 is implemented and enabled in the current Security state. Any of the following apply: EL2 is using AArch64 and HCR_EL2.IMO is 1. EL2 is using AArch32 and HCR.IMO is 1. The PE is executing at EL1. Otherwise, this field shows the pending status of physical IRQ interrupts. 0b0 No pending IRQ. 0b1 An IRQ interrupt is pending. F 6 6 6 FIQ pending bit. Indicates whether an FIQ interrupt is pending. If all of the following apply then this field shows the pending status of virtual FIQ interrupts: EL2 is implemented and enabled in the current Security state. Any of the following apply: EL2 is using AArch64 and HCR_EL2.FMO is 1. EL2 is using AArch32 and HCR.FMO is 1. The PE is executing at EL1. Otherwise, this field shows the pending status of physical FIQ interrupts. 0b0 No pending FIQ. 0b1 An FIQ interrupt is pending. 5 0 5:0 Reserved, RES0. MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); else R(t) = ISR(); end; elsif PSTATE.EL == EL2 then R(t) = ISR(); elsif PSTATE.EL == EL3 then R(t) = ISR(); end; 2026-03-26 20:27:25 2026-03_rel