MAIR1
Memory Attribute Indirection Register 1
when FEAT_AA32EL1 is implemented
MAIR_EL1
Architectural
AArch64
31
0
63
32
31
0
63
32
when EL3 is not implemented or EL3 is using AArch64
NMRR
Architectural
AArch32
31
0
31
0
31
0
31
0
when EL3 is not implemented or EL3 is using AArch64
NMRR
Architectural
AArch32
31
0
MAIR1_NS
31
0
NMRR_NS
31
0
31
0
when EL3 is using AArch32
NMRR
Architectural
AArch32
31
0
MAIR1_S
31
0
NMRR_S
31
0
31
0
when EL3 is using AArch32
Along with MAIR0, provides the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations.
AttrIndx[2] indicates the MAIR register to be used:
When AttrIndx[2] is 0, MAIR0 is used.
When AttrIndx[2] is 1, MAIR1 is used.
Memory
MAIR1 and NMRR are the same register, with a different view depending on the value of TTBCR.EAE:
When it is set to 0, the register is as described in NMRR.
When it is set to 1, the register is as described in MAIR1.
When EL3 is using AArch32, write access to MAIR1(S) is disabled when the CP15SDISABLE signal is asserted HIGH.
This register is banked between MAIR1 and MAIR1_S and MAIR1_NS.
MAIR1 is a 32-bit register.
This register has the following instances:
MAIR1, when EL3 is not implemented or FEAT_AA64 is implemented.
MAIR1_S, when FEAT_AA32EL3 is implemented.
MAIR1_NS, when FEAT_AA32EL3 is implemented.
When TTBCR.EAE == '1'
TTBCR.EAE==1
Attr<n>
31
0
31:0
The memory attribute encoding for an AttrIndx[2:0] entry in a Long descriptor format translation table entry, where:
AttrIndx[2:0] gives the value of <n> in Attr<n>.
AttrIndx[2] defines which MAIR to access. Attr7 to Attr4 are in MAIR1, and Attr3 to Attr0 are in MAIR0.
Bits [7:4] are encoded as follows:
Attr<n>[7:4]Meaning
0b0000Device memory. See encoding of Attr<n>[3:0] for the type of Device memory.
0b00RW, RW not 0b00Normal memory, Outer Write-Through Transient.
0b0100Normal memory, Outer Non-cacheable.
0b01RW, RW not 0b00Normal memory, Outer Write-Back Transient.
0b10RWNormal memory, Outer Write-Through Non-transient.
0b11RWNormal memory, Outer Write-Back Non-transient.
R = Outer Read-Allocate policy, W = Outer Write-Allocate policy.
The meaning of bits [3:0] depends on the value of bits [7:4]:
Attr<n>[3:0]Meaning when Attr<n>[7:4] is 0b0000Meaning when Attr<n>[7:4] is not 0b0000
0b0000Device-nGnRnE memoryUNPREDICTABLE
0b00RW, RW not 0b00UNPREDICTABLENormal memory, Inner Write-Through Transient
0b0100Device-nGnRE memoryNormal memory, Inner Non-cacheable
0b01RW, RW not 0b00UNPREDICTABLENormal memory, Inner Write-Back Transient
0b1000Device-nGRE memoryNormal memory, Inner Write-Through Non-transient (RW=0b00)
0b10RW, RW not 0b00UNPREDICTABLENormal memory, Inner Write-Through Non-transient
0b1100Device-GRE memoryNormal memory, Inner Write-Back Non-transient (RW=0b00)
0b11RW, RW not 0b00UNPREDICTABLENormal memory, Inner Write-Back Non-transient
R = Inner Read-Allocate policy, W = Inner Write-Allocate policy.
The R and W bits in some Attr<n> fields have the following meanings:
R or WMeaning
0b0No Allocate
0b1Allocate
When FEAT_XS is implemented, stage 1 Inner Write-Back Cacheable, Outer Write-Back Cacheable memory types have the XS attribute set to 0.
7
4
AU
When TTBCR.EAE == '1'
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
if !IsFeatureImplemented(FEAT_AA32EL1) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T10 == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T10 == '1' then
AArch32_TakeHypTrapException(0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TRVM == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TRVM == '1' then
AArch32_TakeHypTrapException(0x03);
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then
if TTBCR().EAE == '1' then
R(t) = MAIR1_NS();
else
R(t) = NMRR_NS();
end;
else
if TTBCR().EAE == '1' then
R(t) = MAIR1();
else
R(t) = NMRR();
end;
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then
if TTBCR().EAE == '1' then
R(t) = MAIR1_NS();
else
R(t) = NMRR_NS();
end;
else
if TTBCR().EAE == '1' then
R(t) = MAIR1();
else
R(t) = NMRR();
end;
end;
elsif PSTATE.EL == EL3 then
if TTBCR().EAE == '1' then
if SCR().NS == '0' then
R(t) = MAIR1_S();
else
R(t) = MAIR1_NS();
end;
else
if SCR().NS == '0' then
R(t) = NMRR_S();
else
R(t) = NMRR_NS();
end;
end;
end;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
if !IsFeatureImplemented(FEAT_AA32EL1) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T10 == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T10 == '1' then
AArch32_TakeHypTrapException(0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TVM == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TVM == '1' then
AArch32_TakeHypTrapException(0x03);
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then
if TTBCR().EAE == '1' then
MAIR1_NS() = R(t);
else
NMRR_NS() = R(t);
end;
else
if TTBCR().EAE == '1' then
MAIR1() = R(t);
else
NMRR() = R(t);
end;
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then
if TTBCR().EAE == '1' then
MAIR1_NS() = R(t);
else
NMRR_NS() = R(t);
end;
else
if TTBCR().EAE == '1' then
MAIR1() = R(t);
else
NMRR() = R(t);
end;
end;
elsif PSTATE.EL == EL3 then
if SCR().NS == '0' && CP15SDISABLE == HIGH then
Undefined();
elsif SCR().NS == '0' && CP15SDISABLE2 == HIGH then
Undefined();
else
if TTBCR().EAE == '1' then
if SCR().NS == '0' then
MAIR1_S() = R(t);
else
MAIR1_NS() = R(t);
end;
else
if SCR().NS == '0' then
NMRR_S() = R(t);
else
NMRR_NS() = R(t);
end;
end;
end;
end;
2026-03-26 20:27:25
2026-03_rel