NMRR Normal Memory Remap Register when FEAT_AA32EL1 is implemented MAIR_EL1 Architectural AArch64 31 0 63 32 31 0 63 32 when EL3 is not implemented or EL3 is using AArch64 MAIR1 Architectural AArch32 31 0 31 0 31 0 31 0 when EL3 is not implemented or EL3 is using AArch64 MAIR1 Architectural AArch32 31 0 NMRR_S 31 0 MAIR1_S 31 0 31 0 when EL3 is using AArch32 MAIR1 Architectural AArch32 31 0 NMRR_NS 31 0 MAIR1_NS 31 0 31 0 when EL3 is using AArch32 Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in the PRRR. Used in conjunction with the PRRR. Memory MAIR1 and NMRR are the same register, with a different view depending on the value of TTBCR.EAE: When it is set to 0, the register is as described in NMRR. When it is set to 1, the register is as described in MAIR1. This register is banked between NMRR and NMRR_S and NMRR_NS. NMRR is a 32-bit register. This register has the following instances: NMRR, when EL3 is not implemented or FEAT_AA64 is implemented. NMRR_S, when FEAT_AA32EL3 is implemented. NMRR_NS, when FEAT_AA32EL3 is implemented. When TTBCR.EAE == '0' TTBCR.EAE==0 OR<n> 31 16 31:16 Outer Cacheable property mapping for memory attributes n, if the region is mapped as Normal memory by the PRRR.TR<n> entry. n is the value of the TEX[0], C, and B bits concatenated. The meaning of the field with n = 6 is IMPLEMENTATION DEFINED and might differ from the meaning given here. This is because the meaning of the attribute combination {TEX[0] = 1, C = 1, B = 0} is IMPLEMENTATION DEFINED. When FEAT_XS is implemented, stage 1 Outer Write-Back Cacheable memory types have the XS attribute set to 0. 7 0 0b00 Region is Non-cacheable. 0b01 Region is Write-Back, Write-Allocate. 0b10 Region is Write-Through, no Write-Allocate. 0b11 Region is Write-Back, no Write-Allocate. AU IR<n> 15 0 15:0 Inner Cacheable property mapping for memory attributes n, if the region is mapped as Normal memory by the PRRR.TR<n> entry. n is the value of the TEX[0], C, and B bits concatenated. The meaning of the field with n = 6 is IMPLEMENTATION DEFINED and might differ from the meaning given here. This is because the meaning of the attribute combination {TEX[0] = 1, C = 1, B = 0} is IMPLEMENTATION DEFINED. When FEAT_XS is implemented, stage 1 Inner Write-Back Cacheable memory types have the XS attribute set to 0. 7 0 0b00 Region is Non-cacheable. 0b01 Region is Write-Back, Write-Allocate. 0b10 Region is Write-Through, no Write-Allocate. 0b11 Region is Write-Back, no Write-Allocate. AU When TTBCR.EAE == '0' MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T10 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T10 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TRVM == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TRVM == '1' then AArch32_TakeHypTrapException(0x03); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then if TTBCR().EAE == '1' then R(t) = MAIR1_NS(); else R(t) = NMRR_NS(); end; else if TTBCR().EAE == '1' then R(t) = MAIR1(); else R(t) = NMRR(); end; end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then if TTBCR().EAE == '1' then R(t) = MAIR1_NS(); else R(t) = NMRR_NS(); end; else if TTBCR().EAE == '1' then R(t) = MAIR1(); else R(t) = NMRR(); end; end; elsif PSTATE.EL == EL3 then if TTBCR().EAE == '1' then if SCR().NS == '0' then R(t) = MAIR1_S(); else R(t) = MAIR1_NS(); end; else if SCR().NS == '0' then R(t) = NMRR_S(); else R(t) = NMRR_NS(); end; end; end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T10 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T10 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TVM == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TVM == '1' then AArch32_TakeHypTrapException(0x03); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then if TTBCR().EAE == '1' then MAIR1_NS() = R(t); else NMRR_NS() = R(t); end; else if TTBCR().EAE == '1' then MAIR1() = R(t); else NMRR() = R(t); end; end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then if TTBCR().EAE == '1' then MAIR1_NS() = R(t); else NMRR_NS() = R(t); end; else if TTBCR().EAE == '1' then MAIR1() = R(t); else NMRR() = R(t); end; end; elsif PSTATE.EL == EL3 then if SCR().NS == '0' && CP15SDISABLE == HIGH then Undefined(); elsif SCR().NS == '0' && CP15SDISABLE2 == HIGH then Undefined(); else if TTBCR().EAE == '1' then if SCR().NS == '0' then MAIR1_S() = R(t); else MAIR1_NS() = R(t); end; else if SCR().NS == '0' then NMRR_S() = R(t); else NMRR_NS() = R(t); end; end; end; end; 2026-03-26 20:27:25 2026-03_rel