NSACR Non-Secure Access Control Register when FEAT_AA32EL1 is implemented When EL3 is implemented and can use AArch32, defines the Non-secure access permissions to Trace, Advanced SIMD and floating-point functionality. Also includes IMPLEMENTATION DEFINED bits that can define Non-secure access permissions for IMPLEMENTATION DEFINED functionality. Secure In AArch64 state, the NSACR controls are replaced by controls in CPTR_EL3. NSACR is a 32-bit register. If EL3 is implemented and is using AArch64 then: Any read of the NSACR from Non-secure EL2 or Non-secure EL1 returns a value of 0x00000C00. Any read or write to NSACR from Secure EL1 is trapped as an exception to EL3. If EL3 is not implemented, then any read of the NSACR from EL2 or EL1 returns a value of 0x00000C00. 31 21 31:21 Reserved, RES0. NSTRCDIS 20 20 20 Disables Non-secure System register accesses to all implemented trace System registers. The implementation of this field must correspond to the implementation of the CPACR.TRCDIS field: If CPACR.TRCDIS is RAZ/WI, this field is RAZ/WI. If CPACR.TRCDIS is RW, this field is RW. FEAT_ETMv4 and FEAT_ETE do not permit EL0 to access the trace System registers. EL0 accesses to the trace System registers are UNDEFINED.The Arm architecture does not provide Non-secure access controls on trace register accesses through the optional memory-mapped external debug interface.System register accesses to the trace System registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken. 0b0 This control has no effect on: System register access to implemented trace System registers. The behavior of CPACR.TRCDIS and HCPTR.TTA. 0b1 Non-secure System register accesses to all implemented trace System registers are disabled, meaning: CPACR.TRCDIS behaves as RAO/WI in Non-secure state, regardless of its actual value. HCPTR.TTA behaves as RAO/WI, regardless of its actual value. '0' 19 19 19 Reserved, RES0. IMPLEMENTATION DEFINED 18 16 18:16 IMPLEMENTATION DEFINED. NSASEDIS 15 15 15 Disables Non-secure access to the Advanced SIMD functionality. The implementation of this field must correspond to the implementation of the CPACR.ASEDIS field: If CPACR.ASEDIS is RES0, this field is RES0. If the implementation does not include Advanced SIMD and floating-point functionality, this field is RES0. If CPACR.ASEDIS is RAZ/WI, this field is RAZ/WI. If CPACR.ASEDIS is RW, this field is RW. 0b0 This control has no effect on: Non-secure access to Advanced SIMD functionality. The behavior of CPACR.ASEDIS and HCPTR.TASE. 0b1 Non-secure access to the Advanced SIMD functionality is disabled, meaning: CPACR.ASEDIS behaves as RAO/WI in Non-secure state, regardless of its actual value. HCPTR.TASE behaves as RAO/WI, regardless of its actual value. '0' 14 12 14:12 Reserved, RES0. cp11 11 11 11 The value of this field is ignored. If this field is programmed with a different value to the cp10 field then this field is UNKNOWN on a direct read of the NSACR. If the implementation does not include Advanced SIMD and floating-point functionality, this field is RES0. AU cp10 10 10 10 Enable Non-secure access to the Advanced SIMD and floating-point features. Possible values of the fields are: If Non-secure access to the Advanced SIMD and floating-point functionality is enabled, the CPACR must be checked to determine the level of access that is permitted. The Advanced SIMD and floating-point features controlled by these fields are: Execution of any floating-point or Advanced SIMD instruction. Any access to the Advanced SIMD and floating-point registers D0-D31 and their views as S0-S31 and Q0-Q15. Any access to the FPSCR, FPSID, MVFR0, MVFR1, MVFR2, or FPEXC System registers. If the implementation does not include Advanced SIMD and floating-point functionality, this field is RES0. 0b0 Advanced SIMD and floating-point features can be accessed only from Secure state. Any attempt to access this functionality from Non-secure state is UNDEFINED. When the PE is in Non-secure state: The CPACR.{cp11, cp10} fields ignore writes and read as 0b00, access denied. The HCPTR.{TCP11, TCP10} fields behave as RAO/WI, regardless of their actual values. 0b1 Advanced SIMD and floating-point features can be accessed from both Security states. AU 9 0 9:0 Reserved, RES0. MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T1 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T1 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && IsCurrentSecurityState(SS_Secure) then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && IsCurrentSecurityState(SS_Secure) then AArch64_AArch32SystemAccessTrap(EL3, 0x03); elsif !HaveEL(EL3) || (IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().NS == '1') then R(t) = Zeros{20} :: '1100' :: Zeros{8}; else R(t) = NSACR(); end; elsif PSTATE.EL == EL2 then if !HaveEL(EL3) || (IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().NS == '1') then R(t) = Zeros{20} :: '1100' :: Zeros{8}; else R(t) = NSACR(); end; elsif PSTATE.EL == EL3 then R(t) = NSACR(); end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T1 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T1 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && IsCurrentSecurityState(SS_Secure) then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && IsCurrentSecurityState(SS_Secure) then AArch64_AArch32SystemAccessTrap(EL3, 0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then if CP15SDISABLE2 == HIGH then Undefined(); else NSACR() = R(t); end; end; 2026-03-26 20:27:25 2026-03_rel