PMEVCNTR<n>
Performance Monitors Event Count Registers
when FEAT_AA32 is implemented and FEAT_PMUv3 is implemented
0
30
PMEVCNTR<n>_EL0
Architectural
AArch64
31
0
31
0
31
0
31
0
PMEVCNTR<n>_EL0
Architectural
External
31
0
31
0
31
0
31
0
Holds event counter n, which counts events, where n is 0 to 30.
PMU
PMEVCNTR<n> is a 32-bit register.
EVCNT
Event counter n
31
0
31:0
Event counter n. Value of event counter n, where n is the number of this register and is a number from 0 to 30.
If FEAT_PMUv3p5 is implemented, the event counter is 64 bits and only the least-significant part of the event counter is accessible in AArch32 state:
Reads from PMEVCNTR<n> return bits [31:0] of the counter.
Writes to PMEVCNTR<n> update bits [31:0] and leave bits [63:32] unchanged.
There is no means to access bits [63:32] directly from AArch32 state.
If the implementation does not support AArch64, bits [63:32] are not required to be implemented.
If FEAT_PMUv3p5 is not implemented, the event counter is 32 bits.
AU
AU
PMEVCNTR<n> can also be accessed by using PMXEVCNTR with PMSELR.SEL set to n.
If FEAT_FGT is implemented and <n> is greater than or equal to the number of accessible event counters, then the behavior of permitted reads and writes of PMEVCNTR<n> is as follows:
If <n> is greater than or equal to the Effective value of PMCCR.EPMN, the access is UNDEFINED.
Otherwise, the access is trapped to EL2.
If FEAT_FGT is not implemented and <n> is greater than or equal to the number of accessible event counters, then reads and writes of PMEVCNTR<n> are CONSTRAINED UNPREDICTABLE, and the following behaviors are permitted:
Accesses to the register are UNDEFINED.
Accesses to the register behave as RAZ/WI.
Accesses to the register execute as a NOP.
Accesses to the register behave as if <n> is an UNKNOWN value less-than-or-equal-to the index of the highest accessible event counter.
If EL2 is implemented and enabled in the current Security state, and <n> is less than the number of implemented event counters, accesses from EL1 or permitted accesses from EL0 are trapped to EL2.
Permitted reads and writes of PMEVCNTR<n> are RAZ/WI if all of the following are true:
FEAT_PMUv3p9 is implemented.
EL0 is the current Exception level.
EL1 is using AArch64.
PMUSERENR_EL0.UEN is 1.
PMUACR_EL1.P<n> is 0.
Permitted writes of PMEVCNTR<n> are ignored if all of the following are true:
FEAT_PMUv3p9 is implemented.
EL0 is the current Exception level.
EL1 is using AArch64.
PMUSERENR_EL0.{UEN,ER} is {1,1}.
In EL0, an access is permitted if it is enabled by PMUSERENR.{ER,EN} or PMUSERENR_EL0.{UEN,ER,EN}.If EL2 is implemented and enabled in the current Security state, at EL0 and EL1:If EL2 is using AArch32, HDCR.HPMN identifies the number of accessible event counters.If EL2 is using AArch64, MDCR_EL2.HPMN identifies the number of accessible event counters.
Otherwise, the number of accessible event counters is the number of implemented event counters. For more information, see HDCR.HPMN and MDCR_EL2.HPMN.
0-30
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
let m:integer = UInt(CRm[1:0] :: opc2[2:0]);
if !(IsFeatureImplemented(FEAT_AA32) && IsFeatureImplemented(FEAT_PMUv3)) then
Undefined();
elsif m >= GetNumEventCountersSelfHosted() then
if IsFeatureImplemented(FEAT_FGT) then
Undefined();
else
ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER);
end;
elsif PSTATE.EL == EL0 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TPM == '1' then
Undefined();
elsif IsFeatureImplemented(FEAT_AA64EL1) && !ELUsingAArch32(EL1) && ((IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0().[UEN,ER,EN] == '000') || (!IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0().[ER,EN] == '00')) then
if EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
else
AArch64_AArch32SystemAccessTrap(EL1, 0x03);
end;
elsif IsFeatureImplemented(FEAT_AA32EL1) && ELUsingAArch32(EL1) && PMUSERENR().[ER,EN] == '00' then
if EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && HCR().TGE == '1' then
AArch32_TakeHypTrapException(0x00);
else
Undefined();
end;
elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL1) && !ELUsingAArch32(EL1)) && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().PMEVCNTRn_EL0 == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && MDCR_EL2().TPM == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && HDCR().TPM == '1' then
AArch32_TakeHypTrapException(0x03);
elsif EL2Enabled() && m >= GetNumEventCountersAccessible() then
if !IsFeatureImplemented(FEAT_FGT) then
ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER);
elsif IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) then
AArch32_TakeHypTrapException(0x03);
else
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
end;
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TPM == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x03);
end;
else
if IsFeatureImplemented(FEAT_PMUv3p9) && IsFeatureImplemented(FEAT_AA64EL1) && !ELUsingAArch32(EL2) && PMUSERENR_EL0().UEN == '1' && PMUACR_EL1()[m] == '0' then
R(t) = Zeros{32};
else
R(t) = PMEVCNTR(m);
end;
end;
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TPM == '1' then
Undefined();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && MDCR_EL2().TPM == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HDCR().TPM == '1' then
AArch32_TakeHypTrapException(0x03);
elsif EL2Enabled() && m >= GetNumEventCountersAccessible() then
if !IsFeatureImplemented(FEAT_FGT) then
ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER);
elsif IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) then
AArch32_TakeHypTrapException(0x03);
else
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
end;
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TPM == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x03);
end;
else
R(t) = PMEVCNTR(m);
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TPM == '1' then
Undefined();
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TPM == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x03);
end;
else
R(t) = PMEVCNTR(m);
end;
elsif PSTATE.EL == EL3 then
R(t) = PMEVCNTR(m);
end;
0-30
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
let m:integer = UInt(CRm[1:0] :: opc2[2:0]);
if !(IsFeatureImplemented(FEAT_AA32) && IsFeatureImplemented(FEAT_PMUv3)) then
Undefined();
elsif m >= GetNumEventCountersSelfHosted() then
if IsFeatureImplemented(FEAT_FGT) then
Undefined();
else
ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER);
end;
elsif PSTATE.EL == EL0 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TPM == '1' then
Undefined();
elsif IsFeatureImplemented(FEAT_AA64EL1) && !ELUsingAArch32(EL1) && (PMUSERENR_EL0().EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || PMUSERENR_EL0().UEN == '0')) then
if EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
else
AArch64_AArch32SystemAccessTrap(EL1, 0x03);
end;
elsif IsFeatureImplemented(FEAT_AA32EL1) && ELUsingAArch32(EL1) && PMUSERENR().EN == '0' then
if EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && HCR().TGE == '1' then
AArch32_TakeHypTrapException(0x00);
else
Undefined();
end;
elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL1) && !ELUsingAArch32(EL1)) && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().PMEVCNTRn_EL0 == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && MDCR_EL2().TPM == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && HDCR().TPM == '1' then
AArch32_TakeHypTrapException(0x03);
elsif EL2Enabled() && m >= GetNumEventCountersAccessible() then
if !IsFeatureImplemented(FEAT_FGT) then
ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER);
elsif IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) then
AArch32_TakeHypTrapException(0x03);
else
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
end;
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TPM == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x03);
end;
else
if IsFeatureImplemented(FEAT_PMUv3p9) && IsFeatureImplemented(FEAT_AA64EL1) && !ELUsingAArch32(EL2) && PMUSERENR_EL0().UEN == '1' && (PMUACR_EL1()[m] == '0' || PMUSERENR_EL0().ER == '1') then
return;
else
PMEVCNTR(m) = R(t);
end;
end;
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TPM == '1' then
Undefined();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && MDCR_EL2().TPM == '1' then
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HDCR().TPM == '1' then
AArch32_TakeHypTrapException(0x03);
elsif EL2Enabled() && m >= GetNumEventCountersAccessible() then
if !IsFeatureImplemented(FEAT_FGT) then
ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER);
elsif IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) then
AArch32_TakeHypTrapException(0x03);
else
AArch64_AArch32SystemAccessTrap(EL2, 0x03);
end;
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TPM == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x03);
end;
else
PMEVCNTR(m) = R(t);
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TPM == '1' then
Undefined();
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TPM == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_AArch32SystemAccessTrap(EL3, 0x03);
end;
else
PMEVCNTR(m) = R(t);
end;
elsif PSTATE.EL == EL3 then
PMEVCNTR(m) = R(t);
end;
2026-03-26 20:27:25
2026-03_rel