PRRR Primary Region Remap Register when FEAT_AA32EL1 is implemented MAIR_EL1 Architectural AArch64 31 0 31 0 31 0 31 0 when EL3 is not implemented or EL3 is using AArch64 MAIR0 Architectural AArch32 31 0 31 0 31 0 31 0 when EL3 is not implemented or EL3 is using AArch64 MAIR0 Architectural AArch32 31 0 PRRR_S 31 0 MAIR0_S 31 0 31 0 when EL3 is using AArch32 MAIR0 Architectural AArch32 31 0 PRRR_NS 31 0 MAIR0_NS 31 0 31 0 when EL3 is using AArch32 Controls the top-level mapping of the TEX[0], C, and B memory region attributes. Memory MAIR0 and PRRR are the same register, with a different view depending on the value of TTBCR.EAE: When it is set to 0, the register is as described in PRRR. When it is set to 1, the register is as described in MAIR0. This register is banked between PRRR and PRRR_S and PRRR_NS. PRRR is a 32-bit register. This register has the following instances: PRRR, when EL3 is not implemented or FEAT_AA64 is implemented. PRRR_S, when FEAT_AA32EL3 is implemented. PRRR_NS, when FEAT_AA32EL3 is implemented. When TTBCR.EAE == '0' TTBCR.EAE==0 NOS<n> 31 24 31:24 Not Outer Shareable. NOS<n> is the Outer Shareable property for memory attributes n, if the region is mapped as Normal memory that is not Inner Non-cacheable, Outer Non-cacheable, and the appropriate PRRR.{NS0, NS1} field identifies the region as shareable. n is the value of the concatenation of the {TEX[0], C, B} bits from the Translation table descriptor. The possible values of each NOS<n> field other than NOS6 are: The value of this bit is ignored if the region is: Device memory Normal memory that is at least one of: Inner Non-cacheable, Outer Non-cacheable. Identified by the appropriate PRRR.{NS0, NS1} field as Non-shareable. The meaning of the NOS6 field is IMPLEMENTATION DEFINED. 7 0 0b0 Memory region is Outer Shareable. 0b1 Memory region is Inner Shareable. AU 23 20 23:20 Reserved, RES0. NS1 19 19 19 Mapping of S = 1 attribute for Normal memory regions. This field is used in determining the Shareability of a memory region that is mapped to Normal memory and both: Is not Inner Non-cacheable, Outer Non-cacheable. Has the S bit in the Translation table descriptor set to 1. 0b0 Region is Non-shareable. 0b1 Region is shareable. The value of the appropriate PRRR.NOS<n> field determines whether the region is Inner Shareable or Outer Shareable. AU NS0 18 18 18 Mapping of S = 0 attribute for Normal memory regions. This field is used in determining the Shareability of a memory region that is mapped to Normal memory and both: Is not Inner Non-cacheable, Outer Non-cacheable. Has the S bit in the Translation table descriptor set to 0. 0b0 Region is Non-shareable. 0b1 Region is shareable. The value of the appropriate PRRR.NOS<n> field determines whether the region is Inner Shareable or Outer Shareable. AU DS1 17 17 17 Mapping of S = 1 attribute for Device memory. From Armv8.0, all types of Device memory are Outer Shareable, and therefore this bit is RES1. AU DS0 16 16 16 Mapping of S = 0 attribute for Device memory. From Armv8.0, all types of Device memory are Outer Shareable, and therefore this bit is RES1. AU TR<n> 15 0 15:0 TR<n> is the primary TEX mapping for memory attributes n, and defines the mapped memory type for a region with attributes n. n is the value of the concatenation of the {TEX[0], C, B} bits from the Translation table descriptor. The possible values for each field other than TR6 are: The value 0b11 is reserved. The effect of programming a field to 0b11 is CONSTRAINED UNPREDICTABLE. The meaning of the TR6 field is IMPLEMENTATION DEFINED. When FEAT_XS is implemented, stage 1 Inner Write-Back Cacheable, Outer Write-Back Cacheable memory types have the XS attribute set to 0. 7 0 0b00 Device-nGnRnE memory 0b01 Device-nGnRE memory 0b10 Normal memory AU When TTBCR.EAE == '0' MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T10 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T10 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TRVM == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TRVM == '1' then AArch32_TakeHypTrapException(0x03); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then if TTBCR().EAE == '1' then R(t) = MAIR0_NS(); else R(t) = PRRR_NS(); end; else if TTBCR().EAE == '1' then R(t) = MAIR0(); else R(t) = PRRR(); end; end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then if TTBCR().EAE == '1' then R(t) = MAIR0_NS(); else R(t) = PRRR_NS(); end; else if TTBCR().EAE == '1' then R(t) = MAIR0(); else R(t) = PRRR(); end; end; elsif PSTATE.EL == EL3 then if TTBCR().EAE == '1' then if SCR().NS == '0' then R(t) = MAIR0_S(); else R(t) = MAIR0_NS(); end; else if SCR().NS == '0' then R(t) = PRRR_S(); else R(t) = PRRR_NS(); end; end; end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T10 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T10 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TVM == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TVM == '1' then AArch32_TakeHypTrapException(0x03); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then if TTBCR().EAE == '1' then MAIR0_NS() = R(t); else PRRR_NS() = R(t); end; else if TTBCR().EAE == '1' then MAIR0() = R(t); else PRRR() = R(t); end; end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then if TTBCR().EAE == '1' then MAIR0_NS() = R(t); else PRRR_NS() = R(t); end; else if TTBCR().EAE == '1' then MAIR0() = R(t); else PRRR() = R(t); end; end; elsif PSTATE.EL == EL3 then if SCR().NS == '0' && CP15SDISABLE == HIGH then Undefined(); elsif SCR().NS == '0' && CP15SDISABLE2 == HIGH then Undefined(); else if TTBCR().EAE == '1' then if SCR().NS == '0' then MAIR0_S() = R(t); else MAIR0_NS() = R(t); end; else if SCR().NS == '0' then PRRR_S() = R(t); else PRRR_NS() = R(t); end; end; end; end; 2026-03-26 20:27:25 2026-03_rel