SDCR Secure Debug Control Register when FEAT_AA32EL3 is implemented Provides EL3 configuration options for self-hosted debug, trace, and the Performance Monitors Extension. Secure SDCR is a 32-bit register. 31 29 31:29 Reserved, RES0. MTPME 28 28 0 Multi-threaded PMU Enable. Enables use of the PMEVTYPER<n>.MT bits. If FEAT_MTPMU is disabled for any other PE in the system that has the same level 1 Affinity as the PE, it is IMPLEMENTATION DEFINED whether the PE behaves as if this field is 0. 0b0 FEAT_MTPMU is disabled. The Effective value of PMEVTYPER<n>.MT is 0. 0b1 PMEVTYPER<n>.MT bits not affected by this field. '1' When FEAT_MTPMU is implemented 28 28 28 Reserved, RES0. Otherwise TDCC 27 27 0 Trap DCC. Traps use of the Debug Comms Channel in modes other than Monitor mode to Monitor mode. The DCC registers trapped by this control are: DBGDTRRXext, DBGDTRTXext, DBGDSCRint, DBGDCCINT, and, when the PE is in Non-debug state, DBGDTRRXint and DBGDTRTXint. When the PE is in Debug state, SDCR.TDCC does not trap any accesses to: DBGDTRRXint and DBGDTRTXint. 0b0 This control does not cause any register accesses to be trapped. 0b1 Accesses to the DCC registers in modes other than Monitor mode generate a Monitor Trap exception, unless the access also generates a higher priority exception. Traps on the DCC data transfer registers are ignored when the PE is in Debug state. AU When FEAT_FGT is implemented 27 27 27 Reserved, RES0. Otherwise 26 24 26:24 Reserved, RES0. SCCD 23 23 0 Secure Cycle Counter Disable. Prohibits PMCCNTR from counting in Secure state and EL3. This field does not affect the CPU_CYCLES event or any other event that counts cycles. 0b0 Cycle counting by PMCCNTR is not affected by this mechanism. 0b1 Cycle counting by PMCCNTR is prohibited in Secure state and EL3. '0' When FEAT_PMUv3p5 is implemented 23 23 23 Reserved, RES0. Otherwise 22 22 22 Reserved, RES0. EPMAD 21 21 0 External Performance Monitors Non-secure access disable. Controls Non-secure access to Performance Monitors registers by an external debugger. Otherwise, if EL3 is not implemented and the Effective value of SCR.NS is 0, then the Effective value of this field is 1. 0b0 No accesses from an external debugger to the Performance Monitor registers are prohibited by this control. 0b1 Non-secure accesses from an external debugger to the affected Performance Monitor registers are prohibited. '0' When FEAT_Debugv8p4 is implemented and FEAT_PMUv3_EXT is implemented EPMAD 21 21 0 External Performance Monitors access disable. Controls access to Performance Monitors registers by an external debugger. Otherwise, if EL3 is not implemented and the Effective value of SCR.NS is 0, then the Effective value of this field is 1. 0b0 No accesses from an external debugger to the Performance Monitor registers are prohibited by this control. 0b1 If the IMPLEMENTATION DEFINED authentication interface function ExternalSecureInvasiveDebugEnabled() returns FALSE, then accesses from an external debugger to the affected Performance Monitor registers are prohibited. '0' When FEAT_PMUv3_EXT is implemented 21 21 21 Reserved, RES0. Otherwise EDAD 20 20 0 External debug Non-secure access disable. Controls Non-secure access to breakpoint, watchpoint, and OSLAR_EL1 registers by an external debugger. If EL3 is not implemented and the Effective value of SCR.NS is 0, then the Effective value of this field is 1. 0b0 No accesses from an external debugger to the debug registers are prohibited by this control. 0b1 Non-secure accesses from an external debugger to the affected debug registers are prohibited. '0' When FEAT_Debugv8p4 is implemented EDAD 20 20 0 External debug access disable. Controls access to breakpoint, watchpoint, and OSLAR_EL1 registers by an external debugger. If EL3 is not implemented and the Effective value of SCR.NS is 0, then the Effective value of this field is 1. 0b0 No accesses from an external debugger to the debug registers are prohibited by this control. 0b1 If the IMPLEMENTATION DEFINED authentication interface function ExternalSecureInvasiveDebugEnabled() returns FALSE, then accesses from an external debugger to the affected debug registers are prohibited. '0' When FEAT_Debugv8p2 is implemented EDAD 20 20 0 External debug access disable. Controls access to breakpoint, watchpoint, and optionally OSLAR_EL1 registers by an external debugger. It is IMPLEMENTATION DEFINED whether accesses to OSLAR_EL1 from an external debugger are affected by this control. If EL3 is not implemented and the Effective value of SCR.NS is 0, then the Effective value of this field is 1. 0b0 No accesses from an external debugger to the debug registers are prohibited by this control. 0b1 If the IMPLEMENTATION DEFINED authentication interface function ExternalSecureInvasiveDebugEnabled() returns FALSE, then accesses from an external debugger to the affected debug registers are prohibited. '0' Otherwise TTRF 19 19 0 Trap Trace Filter controls. Controls whether accesses in modes other than Monitor mode to the trace filter control registers generate a Monitor Trap exception. 0b0 Accesses to HTRFCR and TRFCR are not affected by this control bit. 0b1 When not in Monitor mode, accesses to HTRFCR and TRFCR generate a Monitor Trap exception, unless the access generates a higher priority exception. '0' When FEAT_TRF is implemented 19 19 19 Reserved, RES0. Otherwise STE 18 18 0 Secure Trace Enable. This field enables tracing in Secure state and controls the level of authentication required by an external debugger to enable external tracing. This field also controls the level of authentication required by an external debugger to enable external tracing. See 'Register controls to enable self-hosted trace'. If EL3 is not implemented and the Effective value of SCR.NS is 0, the PE behaves as if this field is set to 1. 0b0 Trace is prohibited in Secure state unless overridden by the IMPLEMENTATION DEFINED authentication interface. 0b1 Trace in Secure state is not affected by this field. '0' When FEAT_TRF is implemented 18 18 18 Reserved, RES0. Otherwise SPME 17 17 0 Secure Performance Monitors Enable. Controls event counting in Secure state. This field affects the operation of all event counters in Secure state, and if PMCR.DP is 1, the operation of PMCCNTR in Secure state. When PMCR.DP is 0, PMCCNTR is not affected by this field. If EL3 is not implemented and the Effective value of SCR.NS is 0, then the Effective value of this field is 1. 0b0 Event counting is prohibited in Secure state. If PMCR.DP is 1, PMCCNTR is disabled in Secure state. Otherwise, PMCCNTR is not affected by this mechanism. 0b1 Event counting and PMCCNTR are not affected by this mechanism. '0' When FEAT_PMUv3 is implemented and FEAT_Debugv8p2 is implemented SPME 17 17 0 Secure Performance Monitors Enable. Controls event counting in Secure state. If ExternalSecureNoninvasiveDebugEnabled() is TRUE, the event counters and PMCCNTR are not affected by this field. Otherwise, this field affects the operation of all event counters in Secure state, and if PMCR.DP is 1, the operation of PMCCNTR in Secure state. When PMCR.DP is 0, PMCCNTR is not affected by this field. If EL3 is not implemented and the Effective value of SCR.NS is 0, then the Effective value of this field is 1. 0b0 If ExternalSecureNoninvasiveDebugEnabled() is FALSE, event counting is prohibited in Secure state, and if PMCR.DP is 1, PMCCNTR is disabled in Secure state. 0b1 Event counting and PMCCNTR are not affected by this mechanism. '0' When FEAT_PMUv3 is implemented 17 17 17 Reserved, RES0. Otherwise 16 16 16 Reserved, RES0. SPD 15 14 15:14 AArch32 Secure self-hosted Privileged Debug. Enables or disables debug exceptions from EL3, other than Breakpoint Instruction exceptions. Other values are reserved, and have the CONSTRAINED UNPREDICTABLE behavior that they must have the same behavior as 0b00. Software must not rely on this property as the behavior of reserved values might change in a future revision of the architecture. This field has no effect on Breakpoint Instruction exceptions. These are always enabled. This field is ignored in Non-secure state. If debug exceptions from EL3 are enabled, then debug exceptions from Secure EL0 are also enabled. Otherwise, debug exceptions from Secure EL0 are enabled only if the value of SDER.SUIDEN is 1. If EL3 is not implemented and the Effective value of SCR.NS is 0, then the Effective value of this field is 0b11. 0b00 Legacy mode. Debug exceptions from EL3 are enabled by the authentication interface. 0b10 Secure privileged debug disabled. Debug exceptions from EL3 are disabled. 0b11 Secure privileged debug enabled. Debug exceptions from EL3 are enabled. '00' 13 0 13:0 Reserved, RES0. MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL3) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T1 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T1 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && IsCurrentSecurityState(SS_Secure) then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && IsCurrentSecurityState(SS_Secure) then AArch64_AArch32SystemAccessTrap(EL3, 0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then R(t) = SDCR(); end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL3) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T1 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T1 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && IsCurrentSecurityState(SS_Secure) then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && IsCurrentSecurityState(SS_Secure) then AArch64_AArch32SystemAccessTrap(EL3, 0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then if CP15SDISABLE2 == HIGH then Undefined(); else SDCR() = R(t); end; end; 2026-03-26 20:27:25 2026-03_rel