SPSR_hyp Saved Program Status Register (Hyp mode) when FEAT_AA32EL2 is implemented SPSR_EL2 Architectural AArch64 31 0 31 0 31 0 31 0 Holds the saved process state when an exception is taken to Hyp mode. Special SPSR_hyp is a 32-bit register. N 31 31 31 Negative Condition flag. Set to the value of PSTATE.N on taking an exception to Hyp mode, and copied to PSTATE.N on executing an exception return operation in Hyp mode. AU Z 30 30 30 Zero Condition flag. Set to the value of PSTATE.Z on taking an exception to Hyp mode, and copied to PSTATE.Z on executing an exception return operation in Hyp mode. AU C 29 29 29 Carry Condition flag. Set to the value of PSTATE.C on taking an exception to Hyp mode, and copied to PSTATE.C on executing an exception return operation in Hyp mode. AU V 28 28 28 Overflow Condition flag. Set to the value of PSTATE.V on taking an exception to Hyp mode, and copied to PSTATE.V on executing an exception return operation in Hyp mode. AU Q 27 27 27 Overflow or saturation flag. Set to the value of PSTATE.Q on taking an exception to Hyp mode, and copied to PSTATE.Q on executing an exception return operation in Hyp mode. AU IT 26 25 15:10, 26:25 If-Then. Set to the value of PSTATE.IT on taking an exception to Hyp mode, and copied to PSTATE.IT on executing an exception return operation in Hyp mode. On executing an exception return operation in Hyp mode, SPSR_hyp.IT must contain a value that is valid for the instruction being returned to. The IT field is split as follows: IT[1:0] is SPSR_hyp[26:25]. IT[7:2] is SPSR_hyp[15:10]. 15 10 26 25 AU J 24 24 24 RES0. In previous versions of the architecture, the {J, T} bits determined the AArch32 Instruction set state. Armv8 does not support either Jazelle state or T32EE state, and the T bit determines the Instruction set state. SSBS 23 23 0 Speculative Store Bypass. Set to the value of PSTATE.SSBS on taking an exception to Hyp mode, and copied to PSTATE.SSBS on executing an exception return operation in Hyp mode. AU When FEAT_SSBS is implemented 23 23 23 Reserved, RES0. Otherwise PAN 22 22 0 Privileged Access Never. Set to the value of PSTATE.PAN on taking an exception to Hyp mode, and copied to PSTATE.PAN on executing an exception return operation in Hyp mode. AU When FEAT_PAN is implemented 22 22 22 Reserved, RES0. Otherwise DIT 21 21 0 Data Independent Timing. Set to the value of PSTATE.DIT on taking an exception to Hyp mode, and copied to PSTATE.DIT on executing an exception return operation in Hyp mode. AU When FEAT_DIT is implemented 21 21 21 Reserved, RES0. Otherwise IL 20 20 20 Illegal Execution state. Set to the value of PSTATE.IL on taking an exception to Hyp mode, and copied to PSTATE.IL on executing an exception return operation in Hyp mode. AU GE 19 16 19:16 Greater than or Equal flags. Set to the value of PSTATE.GE on taking an exception to Hyp mode, and copied to PSTATE.GE on executing an exception return operation in Hyp mode. AU IT[7:2] 15 10 15:10, 26:25 This field is bits[7:2] of IT[7:0]. See IT[1:0] for the field description. E 9 9 9 Endianness. Set to the value of PSTATE.E on taking an exception to Hyp mode, and copied to PSTATE.E on executing an exception return operation in Hyp mode. If the implementation does not support big-endian operation, SPSR_hyp.E is RES0. If the implementation does not support little-endian operation, SPSR_hyp.E is RES1. On executing an exception return operation in Hyp mode, if the implementation does not support big-endian operation at the Exception level being returned to, SPSR_hyp.E is RES0, and if the implementation does not support little-endian operation at the Exception level being returned to, SPSR_hyp.E is RES1. AU A 8 8 8 SError exception mask. Set to the value of PSTATE.A on taking an exception to Hyp mode, and copied to PSTATE.A on executing an exception return operation in Hyp mode. AU I 7 7 7 IRQ interrupt mask. Set to the value of PSTATE.I on taking an exception to Hyp mode, and copied to PSTATE.I on executing an exception return operation in Hyp mode. AU F 6 6 6 FIQ interrupt mask. Set to the value of PSTATE.F on taking an exception to Hyp mode, and copied to PSTATE.F on executing an exception return operation in Hyp mode. AU T 5 5 5 T32 Instruction set state. Set to the value of PSTATE.T on taking an exception to Hyp mode, and copied to PSTATE.T on executing an exception return operation in Hyp mode. AU M[4:0] 4 0 4:0 Mode. Set to the value of PSTATE.M[4:0] on taking an exception to Hyp mode, and copied to PSTATE.M[4:0] on executing an exception return operation in Hyp mode. Other values are reserved. If SPSR_hyp.M[4:0] has a Reserved value, or a value for an unimplemented Exception level, executing an exception return operation in Hyp mode is an illegal return event, as described in 'Illegal return events from AArch32 state'. 0b10000 User. 0b10001 FIQ. 0b10010 IRQ. 0b10011 Supervisor. 0b10111 Abort. 0b11010 Hyp. When FEAT_EL3 is implemented 0b11011 Undefined. 0b11111 System. AU SPSR_hyp is accessible only in Monitor mode. The MSR (register) and MRS instructions used to access SPSR_hyp are data-independent-time instructions as described in About PSTATE.DIT. MRS{<c>}{<q>} <Rd>, SPSR_hyp MSR{<c>}{<q>} SPSR_hyp, <Rn> 2026-03-26 20:27:25 2026-03_rel