Address Translate Stages 1 and 2 Non-secure Only PL1 Read Address Translate Stages 1 and 2 Non-secure Only PL1 Write Address Translate Stages 1 and 2 Non-secure Only Unprivileged Read Address Translate Stages 1 and 2 Non-secure Only Unprivileged Write Address Translate Stage 1 Current state PL1 Read Address Translate Stage 1 Current state PL1 Read PAN Address Translate Stage 1 Current state PL1 Write Address Translate Stage 1 Current state PL1 Write PAN Address Translate Stage 1 Current state Unprivileged Read Address Translate Stage 1 Current state Unprivileged Write Address Translate Stage 1 Hyp mode Read Address Translate Stage 1 Hyp mode Write Branch Predictor Invalidate All Branch Predictor Invalidate All, Inner Shareable Branch Predictor Invalidate by VA Control Flow Prediction Restriction by Context Clear Other Speculative Prediction Restriction by Context Data Memory Barrier System instruction Data Synchronization Barrier System instruction Instruction Synchronization Barrier System instruction Cache Prefetch Prediction Restriction by Context Data Cache line Clean and Invalidate by VA to PoC Data Cache line Clean and Invalidate by Set/Way Data Cache line Clean by VA to PoC Data Cache line Clean by VA to PoU Data Cache line Clean by Set/Way Data Cache line Invalidate by VA to PoC Data Cache line Invalidate by Set/Way Data TLB Invalidate All Data TLB Invalidate by ASID match Data TLB Invalidate by VA Data Value Prediction Restriction by Context Instruction Cache Invalidate All to PoU Instruction Cache Invalidate All to PoU, Inner Shareable Instruction Cache line Invalidate by VA to PoU Instruction TLB Invalidate All Instruction TLB Invalidate by ASID match Instruction TLB Invalidate by VA TLB Invalidate All TLB Invalidate All, Hyp mode TLB Invalidate All, Hyp mode, Inner Shareable TLB Invalidate All, Inner Shareable TLB Invalidate All, Non-Secure Non-Hyp TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable TLB Invalidate by ASID match TLB Invalidate by ASID match, Inner Shareable TLB Invalidate by Intermediate Physical Address, Stage 2 TLB Invalidate by Intermediate Physical Address, Stage 2, Inner Shareable TLB Invalidate by Intermediate Physical Address, Stage 2, Last level TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, Inner Shareable TLB Invalidate by VA TLB Invalidate by VA, All ASID TLB Invalidate by VA, All ASID, Inner Shareable TLB Invalidate by VA, All ASID, Last level TLB Invalidate by VA, All ASID, Last level, Inner Shareable TLB Invalidate by VA, Hyp mode TLB Invalidate by VA, Hyp mode, Inner Shareable TLB Invalidate by VA, Inner Shareable TLB Invalidate by VA, Last level TLB Invalidate by VA, Last level, Hyp mode TLB Invalidate by VA, Last level, Hyp mode, Inner Shareable TLB Invalidate by VA, Last level, Inner Shareable 2026-03-26 20:27:25 2026-03_rel