TLBIALLNSNHIS TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable when FEAT_AA32EL2 is implemented If EL2 is implemented, invalidate all cached copies of translation table entries from TLBs that are from any level of the translation table walk that would be required for stage 1 or stage 2 of the Non-secure PL1&0 translation regime, regardless of the associated VMID. The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this System instruction. TLB TLBIALLNSNHIS is a 32-bit System instruction. If this instruction is executed in a Secure privileged mode other than Monitor mode, then the behavior is CONSTRAINED UNPREDICTABLE, and one of the following behaviors must occur: The instruction is UNDEFINED. The instruction is treated as a NOP. The instruction executes as if it had been executed in Monitor mode. MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL2) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T8 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T8 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then AArch32_TLBI_ALL(SecurityStateAtEL(EL1), Regime_EL10, Broadcast_ISH, TLBI_AllAttr); elsif PSTATE.EL == EL3 then if !HaveEL(EL2) then Undefined(); else AArch32_TLBI_ALL(SS_NonSecure, Regime_EL10, Broadcast_ISH, TLBI_AllAttr); end; end; 2026-03-26 20:27:25 2026-03_rel