TTBCR Translation Table Base Control Register when FEAT_AA32EL1 is implemented Some RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch32. If the PE resets into EL3 using AArch32, then: The EAE bit resets to 0 in both the Secure and the Non-secure instances of the register. Other reset values apply only to the Secure instance of the register. TCR_EL1 Architectural AArch64 31 0 31 0 31 0 31 0 The control register for stage 1 of the PL1&0 translation regime. Its controls include: Where the VA range is split between addresses translated using TTBR0 and addresses translated using TTBR1. The translation table format used by this stage of translation. From Armv8.2, when the value of TTBCR.{EAE, T2E} is {1, 1}, TTBCR is used with TTBCR2. Memory The current translation table format determines which format of the register is used. Some RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch32. If the PE resets into EL3 using AArch32, then: The EAE bit resets to 0 in both the Secure and the Non-secure instances of the register. Other reset values apply only to the Secure instance of the register. This register is banked between TTBCR and TTBCR_S and TTBCR_NS. TTBCR is a 32-bit register. This register has the following instances: TTBCR, when EL3 is not implemented or FEAT_AA64 is implemented. TTBCR_S, when FEAT_AA32EL3 is implemented. TTBCR_NS, when FEAT_AA32EL3 is implemented. When TTBCR.EAE == '0' AArch32-TTBCR.EAE == 0 EAE 31 31 31 Extended Address Enable. 0b0 Use the VMSAv8-32 translation system with the Short-descriptor translation table format. '0' 30 6 30:6 Reserved, RES0. PD1 5 5 5 Translation table walk disable for translations using TTBR1. This bit controls whether a translation table walk is performed on a TLB miss, for an address that is translated using TTBR1. 0b0 Perform translation table walks using TTBR1. 0b1 A TLB miss on an address that is translated using TTBR1 generates a Translation fault. No translation table walk is performed. '0' PD0 4 4 4 Translation table walk disable for translations using TTBR0. This bit controls whether a translation table walk is performed on a TLB miss for an address that is translated using TTBR0. 0b0 Perform translation table walks using TTBR0. 0b1 A TLB miss on an address that is translated using TTBR0 generates a Translation fault. No translation table walk is performed. '0' 3 3 3 Reserved, RES0. N 2 0 2:0 Indicate the width of the base address held in TTBR0. In TTBR0, the base address field is bits[31:14-N]. The value of N also determines: Whether TTBR0 or TTBR1 is used as the base address for translation table walks. The size of the translation table pointed to by TTBR0. N can take any value from 0 to 7, that is, from 0b000 to 0b111. When N has its reset value of 0, the translation table base is compatible with Armv5 and Armv6. '000' When TTBCR.EAE == '1' AArch32-TTBCR.EAE==1 EAE 31 31 31 Extended Address Enable. 0b1 Use the VMSAv8-32 translation system with the Long-descriptor translation table format. '0' IMPLEMENTATION DEFINED 30 30 30 IMPLEMENTATION DEFINED. '0' SH1 29 28 29:28 Shareability attribute for memory associated with translation table walks using TTBR1. Other values are reserved. The effect of programming this field to a Reserved value is that behavior is CONSTRAINED UNPREDICTABLE. 0b00 Non-shareable. 0b10 Outer Shareable. 0b11 Inner Shareable. '00' ORGN1 27 26 27:26 Outer cacheability attribute for memory associated with translation table walks using TTBR1. 0b00 Normal memory, Outer Non-cacheable. 0b01 Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable. 0b10 Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable. 0b11 Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable. '00' IRGN1 25 24 25:24 Inner cacheability attribute for memory associated with translation table walks using TTBR1. 0b00 Normal memory, Inner Non-cacheable. 0b01 Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable. 0b10 Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable. 0b11 Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable. '00' EPD1 23 23 23 Translation table walk disable for translations using TTBR1. This bit controls whether a translation table walk is performed on a TLB miss, for an address that is translated using TTBR1. 0b0 Perform translation table walks using TTBR1. 0b1 A TLB miss on an address that is translated using TTBR1 generates a Translation fault. No translation table walk is performed. '0' A1 22 22 22 Selects whether TTBR0 or TTBR1 defines the ASID. 0b0 TTBR0.ASID defines the ASID. 0b1 TTBR1.ASID defines the ASID. '0' 21 19 21:19 Reserved, RES0. T1SZ 18 16 18:16 See 'Selecting between TTBR0 and TTBR1, VMSAv8-32 Long-descriptor translation table format' for how TTBCR.{T1SZ, T0SZ} determine the input address ranges and memory region sizes translated using TTBR0 and TTBR1. '000' 15 14 15:14 Reserved, RES0. SH0 13 12 13:12 Shareability attribute for memory associated with translation table walks using TTBR0. Other values are reserved. The effect of programming this field to a Reserved value is that behavior is CONSTRAINED UNPREDICTABLE. 0b00 Non-shareable 0b10 Outer Shareable 0b11 Inner Shareable '00' ORGN0 11 10 11:10 Outer cacheability attribute for memory associated with translation table walks using TTBR0. 0b00 Normal memory, Outer Non-cacheable. 0b01 Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable. 0b10 Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable. 0b11 Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable. '00' IRGN0 9 8 9:8 Inner cacheability attribute for memory associated with translation table walks using TTBR0. 0b00 Normal memory, Inner Non-cacheable. 0b01 Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable. 0b10 Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable. 0b11 Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable. '00' EPD0 7 7 7 Translation table walk disable for translations using TTBR0. This bit controls whether a translation table walk is performed on a TLB miss, for an address that is translated using TTBR0. 0b0 Perform translation table walks using TTBR0. 0b1 A TLB miss on an address that is translated using TTBR0 generates a Translation fault. No translation table walk is performed. '0' T2E 6 6 0 TTBCR2 Enable. If TTBCR.EAE==0, then the behavior is as if the bit is 0. 0b0 TTBCR2 is disabled. The contents of TTBCR2 are treated as 0 for all purposes other than reading or writing the register. 0b1 TTBCR2 is enabled. When FEAT_AA32HPD is implemented 6 6 6 Reserved, RES0. Otherwise 5 3 5:3 Reserved, RES0. T0SZ 2 0 2:0 See 'Selecting between TTBR0 and TTBR1, VMSAv8-32 Long-descriptor translation table format' for how TTBCR.{T1SZ, T0SZ} determine the input address ranges and memory region sizes translated using TTBR0 and TTBR1. '000' When TTBCR.EAE == '0' When TTBCR.EAE == '1' MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T2 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T2 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TRVM == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TRVM == '1' then AArch32_TakeHypTrapException(0x03); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then R(t) = TTBCR_NS(); else R(t) = TTBCR(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then R(t) = TTBCR_NS(); else R(t) = TTBCR(); end; elsif PSTATE.EL == EL3 then if SCR().NS == '0' then R(t) = TTBCR_S(); else R(t) = TTBCR_NS(); end; end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T2 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T2 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TVM == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TVM == '1' then AArch32_TakeHypTrapException(0x03); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then TTBCR_NS() = R(t); else TTBCR() = R(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then TTBCR_NS() = R(t); else TTBCR() = R(t); end; elsif PSTATE.EL == EL3 then if SCR().NS == '0' && CP15SDISABLE == HIGH then Undefined(); elsif SCR().NS == '0' && CP15SDISABLE2 == HIGH then Undefined(); else if SCR().NS == '0' then TTBCR_S() = R(t); else TTBCR_NS() = R(t); end; end; end; 2026-03-26 20:27:25 2026-03_rel