VDFSR Virtual SError Exception Syndrome Register when FEAT_RAS is implemented and FEAT_AA32EL1 is implemented VSESR_EL2 Architectural AArch64 31 0 31 0 31 0 31 0 Provides the syndrome value reported to software on taking a virtual SError exception exception to EL1, or on executing an ESB instruction at EL1. When the virtual SError exception injected using HCR.VA is taken to EL1 using AArch32, then the syndrome value is reported in DFSR.{AET, ExT} and the remainder of DFSR is set as defined by VMSAv8-32. For more information, see The AArch32 Virtual Memory System Architecture. If the virtual SError exception injected using HCR.VA is deferred by an ESB instruction, then the syndrome value is written to VDISR. RAS If EL2 is not implemented, then VDFSR is RES0 from Monitor mode when SCR.NS == 1. VDFSR is a 32-bit register. 31 16 31:16 Reserved, RES0. AET 15 14 15:14 When a virtual SError exception is taken to EL1 using AArch32, DFSR[15:14] is set to VDFSR.AET. When a virtual SError exception is deferred by an ESB instruction, VDISR[15:14] is set to VDFSR.AET. AU 13 13 13 Reserved, RES0. ExT 12 12 12 When a virtual SError exception is taken to EL1 using AArch32, DFSR[12] is set to VDFSR.ExT. When a virtual SError exception is deferred by an ESB instruction, VDISR[12] is set to VDFSR.ExT. AU 11 0 11:0 Reserved, RES0. Direct reads and writes of VDFSR are UNDEFINED if EL3 is implemented and using AArch32 in all Secure privileged modes other than Monitor mode. If EL2 is not implemented, then VDFSR is RES0 from Monitor mode when SCR.NS == 1. MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !(IsFeatureImplemented(FEAT_RAS) && IsFeatureImplemented(FEAT_AA32EL1)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T5 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T5 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then R(t) = VDFSR(); elsif PSTATE.EL == EL3 then if SCR().NS == '0' then Undefined(); else R(t) = VDFSR(); end; end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !(IsFeatureImplemented(FEAT_RAS) && IsFeatureImplemented(FEAT_AA32EL1)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T5 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T5 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then VDFSR() = R(t); elsif PSTATE.EL == EL3 then if SCR().NS == '0' then Undefined(); else VDFSR() = R(t); end; end; 2026-03-26 20:27:25 2026-03_rel