VDISR Virtual Deferred Interrupt Status Register when FEAT_AA32EL1 is implemented and FEAT_RAS is implemented VDISR_EL2 Architectural AArch64 31 0 31 0 31 0 31 0 Records that an SError exception has been consumed by an ESB instruction. RAS If EL2 is not implemented, then VDISR is RES0 from Monitor mode when SCR.NS == 1. VDISR is a 32-bit register. When TTBCR.EAE == '0' A 31 31 31 Set to 1 when an ESB instruction defers a virtual SError exception. AU 30 16 30:16 Reserved, RES0. AET 15 14 15:14 The value copied from VDFSR.AET. AU 13 13 13 Reserved, RES0. ExT 12 12 12 The value copied from VDFSR.ExT. AU 11 11 11 Reserved, RES0. FS 10 10 10, 3:0 Fault status code. Set to 0b10110 when an ESB instruction defers a virtual SError exception. All other values are reserved. The FS field is split as follows: FS[4] is VDISR[10]. FS[3:0] is VDISR[3:0]. 10 10 3 0 FS 0b10110 Asynchronous SError exception. AU LPAE 9 9 9 Format. Set to TTBCR.EAE when an ESB instruction defers a virtual SError exception. 0b0 Using the Short-descriptor translation table format. AU 8 4 8:4 Reserved, RES0. FS[3:0] 3 0 10, 3:0 This field is bits[3:0] of FS[4:0]. See FS[4] for the field description. When TTBCR.EAE == '1' A 31 31 31 Set to 1 when an ESB instruction defers a virtual SError exception. AU 30 16 30:16 Reserved, RES0. AET 15 14 15:14 The value copied from VDFSR.AET. AU 13 13 13 Reserved, RES0. ExT 12 12 12 The value copied from VDFSR.ExT. AU 11 10 11:10 Reserved, RES0. LPAE 9 9 9 Format. Set to TTBCR.EAE when an ESB instruction defers a virtual SError exception. 0b1 Using the Long-descriptor translation table format. AU 8 6 8:6 Reserved, RES0. STATUS 5 0 5:0 Fault status code. Set to 0b010001 when an ESB instruction defers a virtual SError exception. All other values are reserved. 0b010001 Asynchronous SError exception. AU When TTBCR.EAE == '0' When TTBCR.EAE == '1' Direct reads and writes of VDFSR are UNDEFINED if EL3 is implemented and using AArch32 in all Secure privileged modes other than Monitor mode. An indirect write to VDISR made by an ESB instruction does not require an explicit synchronization operation for the value that is written to be observed by a direct read of DISR occurring in program order after the ESB instruction. If EL2 is not implemented, then VDISR is RES0 from Monitor mode when SCR.NS == 1. MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !(IsFeatureImplemented(FEAT_AA32EL1) && IsFeatureImplemented(FEAT_RAS)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then R(t) = VDISR(); elsif PSTATE.EL == EL3 then if SCR().NS == '0' then Undefined(); else R(t) = VDISR(); end; end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !(IsFeatureImplemented(FEAT_AA32EL1) && IsFeatureImplemented(FEAT_RAS)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then VDISR() = R(t); elsif PSTATE.EL == EL3 then if SCR().NS == '0' then Undefined(); else VDISR() = R(t); end; end; MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !(IsFeatureImplemented(FEAT_RAS) && IsFeatureImplemented(FEAT_AA32EL1)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && (HCR_EL2().AMO == '1' || (IsFeatureImplemented(FEAT_DoubleFault2) && IsHCRXEL2Enabled() && HCRX_EL2().TMEA == '1')) then R(t) = VDISR_EL2()[31:0]; elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().AMO == '1' then R(t) = VDISR(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && !Halted() && SCR_EL3().EA == '1' then R(t) = Zeros{32}; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && !Halted() && SCR().EA == '1' then R(t) = Zeros{32}; else R(t) = DISR(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && !Halted() && SCR_EL3().EA == '1' then R(t) = Zeros{32}; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && !Halted() && SCR().EA == '1' then R(t) = Zeros{32}; else R(t) = DISR(); end; elsif PSTATE.EL == EL3 then R(t) = DISR(); end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !(IsFeatureImplemented(FEAT_RAS) && IsFeatureImplemented(FEAT_AA32EL1)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && (HCR_EL2().AMO == '1' || (IsFeatureImplemented(FEAT_DoubleFault2) && IsHCRXEL2Enabled() && HCRX_EL2().TMEA == '1')) then VDISR_EL2()[31:0] = R(t); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().AMO == '1' then VDISR() = R(t); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && !Halted() && SCR_EL3().EA == '1' then return; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && !Halted() && SCR().EA == '1' then return; else DISR() = R(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && !Halted() && SCR_EL3().EA == '1' then return; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && !Halted() && SCR().EA == '1' then return; else DISR() = R(t); end; elsif PSTATE.EL == EL3 then DISR() = R(t); end; 2026-03-26 20:27:25 2026-03_rel