VMPIDR Virtualization Multiprocessor ID Register when FEAT_AA32EL2 is implemented EL2 EL3 VMPIDR_EL2 Architectural AArch64 31 0 31 0 31 0 31 0 Holds the value of the Virtualization Multiprocessor ID. This is the value returned by Non-secure EL1 reads of MPIDR, which in a multiprocessor system, provides an additional PE identification system. Virt If EL2 is not implemented but EL3 is implemented, this register takes the value of the MPIDR. VMPIDR is a 32-bit register. M 31 31 31 Indicates whether this implementation includes the functionality introduced by the Armv7 Multiprocessing Extensions. 0b0 This implementation does not include the Armv7 Multiprocessing Extensions functionality. 0b1 This implementation includes the Armv7 Multiprocessing Extensions functionality. RES1 U 30 30 30 Indicates a Uniprocessor system, as distinct from PE 0 in a multiprocessor system. 0b0 Processor is part of a multiprocessor system. 0b1 Processor is part of a uniprocessor system. MPIDR U AU 29 25 29:25 Reserved, RES0. MT 24 24 24 Indicates whether the lowest level of affinity consists of logical PEs that are implemented using a multithreading type approach. See the description of Aff0 for more information about affinity levels. 0b0 Performance of PEs at the lowest affinity level is largely independent. 0b1 Performance of PEs at the lowest affinity level is very interdependent. MPIDR MT AU Aff2 23 16 23:16 Affinity level 2. See the description of Aff0 for more information. MPIDR Aff2 AU Aff1 15 8 15:8 Affinity level 1. See the description of Aff0 for more information. MPIDR Aff1 AU Aff0 7 0 7:0 Affinity level 0. The value of the MPIDR.{Aff2, Aff1, Aff0} or MPIDR_EL1.{Aff3, Aff2, Aff1, Aff0} set of fields of each PE must be unique within the system as a whole. MPIDR Aff0 AU MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL2) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T0 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T0 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then R(t) = VMPIDR(); elsif PSTATE.EL == EL3 then if !HaveEL(EL2) then R(t) = MPIDR(); elsif SCR().NS == '0' then Undefined(); else R(t) = VMPIDR(); end; end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL2) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T0 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T0 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then VMPIDR() = R(t); elsif PSTATE.EL == EL3 then if !HaveEL(EL2) then return; elsif SCR().NS == '0' then Undefined(); else VMPIDR() = R(t); end; end; MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T0 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T0 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) then R(t) = VMPIDR_EL2()[31:0]; elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) then R(t) = VMPIDR(); else R(t) = MPIDR(); end; elsif PSTATE.EL == EL2 then R(t) = MPIDR(); elsif PSTATE.EL == EL3 then R(t) = MPIDR(); end; 2026-03-26 20:27:25 2026-03_rel