VPIDR Virtualization Processor ID Register when FEAT_AA32EL2 is implemented EL2 EL3 VPIDR_EL2 Architectural AArch64 31 0 31 0 31 0 31 0 Holds the value of the Virtualization Processor ID. This is the value returned by Non-secure EL1 reads of MIDR. Virt If EL2 is not implemented but EL3 is implemented, this register takes the value of the MIDR. VPIDR is a 32-bit register. Implementer 31 24 31:24 The Implementer code. This field must hold an implementer code that has been assigned by Arm. Arm can assign codes that are not published in this manual. All values not assigned by Arm are reserved and must not be used. 0x00 Reserved for software use. 0x41 Arm Limited. 0x42 Broadcom Corporation. 0x43 Cavium Inc. 0x44 Digital Equipment Corporation. 0x46 Fujitsu Ltd. 0x49 Infineon Technologies AG. 0x4D Motorola or Freescale Semiconductor Inc. 0x4E NVIDIA Corporation. 0x50 Applied Micro Circuits Corporation. 0x51 Qualcomm Inc. 0x56 Marvell International Ltd. 0x69 Intel Corporation. 0xC0 Ampere Computing. MIDR Implementer AU Variant 23 20 23:20 An IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product. MIDR Variant AU Architecture 19 16 19:16 Architecture version. All other values are reserved. 0b0001 Armv4. 0b0010 Armv4T. 0b0011 Armv5 (obsolete). 0b0100 Armv5T. 0b0101 Armv5TE. 0b0110 Armv5TEJ. 0b0111 Armv6. 0b1111 Architectural features are individually identified in the ID_* registers. MIDR Architecture AU PartNum 15 4 15:4 An IMPLEMENTATION DEFINED primary part number for the device. On processors implemented by Arm, if the top four bits of the primary part number are 0x0 or 0x7, the variant and architecture are encoded differently. MIDR PartNum AU Revision 3 0 3:0 An IMPLEMENTATION DEFINED revision number for the device. MIDR Revision AU MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL2) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T0 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T0 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then R(t) = VPIDR(); elsif PSTATE.EL == EL3 then if !HaveEL(EL2) then R(t) = MIDR(); elsif SCR().NS == '0' then Undefined(); else R(t) = VPIDR(); end; end; MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL2) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T0 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T0 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then VPIDR() = R(t); elsif PSTATE.EL == EL3 then if !HaveEL(EL2) then return; elsif SCR().NS == '0' then Undefined(); else VPIDR() = R(t); end; end; MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T0 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T0 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) then R(t) = VPIDR_EL2()[31:0]; elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) then R(t) = VPIDR(); else R(t) = MIDR(); end; elsif PSTATE.EL == EL2 then R(t) = MIDR(); elsif PSTATE.EL == EL3 then R(t) = MIDR(); end; 2026-03-26 20:27:25 2026-03_rel