AFSR1_EL2 Auxiliary Fault Status Register 1 (EL2) when FEAT_AA64 is implemented HAIFSR Architectural AArch32 31 0 31 0 31 0 31 0 Provides additional IMPLEMENTATION DEFINED fault status information for exceptions taken to EL2. IMP DEF Virt Exception If EL2 is not implemented, this register is RES0 from EL3. This register has no effect if EL2 is not enabled in the current Security state. AFSR1_EL2 is a 64-bit register. IMPLEMENTATION DEFINED 63 0 63:0 IMPLEMENTATION DEFINED. AU When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the accessor name AFSR1_EL2 or AFSR1_EL1 are not guaranteed to be ordered with respect to accesses using the other accessor name. MRS <Xt>, AFSR1_EL2 if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then X{64}(t) = AFSR1_EL2(); elsif PSTATE.EL == EL3 then X{64}(t) = AFSR1_EL2(); end; MSR AFSR1_EL2, <Xt> if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then AFSR1_EL2() = X{64}(t); elsif PSTATE.EL == EL3 then AFSR1_EL2() = X{64}(t); end; MRS <Xt>, AFSR1_EL1 When FEAT_VHE is implemented if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().TRVM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().AFSR1_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x130); else X{64}(t) = AFSR1_EL1(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then X{64}(t) = AFSR1_EL2(); else X{64}(t) = AFSR1_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = AFSR1_EL1(); end; MSR AFSR1_EL1, <Xt> When FEAT_VHE is implemented if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().TVM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().AFSR1_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x130) = X{64}(t); else AFSR1_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then AFSR1_EL2() = X{64}(t); else AFSR1_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then AFSR1_EL1() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel