AMCFGR_EL0 Activity Monitors Configuration Register when FEAT_AMUv1 is implemented AMCFGR Architectural AArch32 31 0 31 0 31 0 31 0 AMCFGR Architectural External 31 0 31 0 31 0 31 0 when FEAT_AMU_EXT32 is implemented AMCFGR Architectural External 63 0 63 0 63 0 63 0 when FEAT_AMU_EXT64 is implemented Global configuration register for the activity monitors. Provides information on supported features, the number of counter groups implemented, the total number of activity monitor event counters implemented, and the size of the counters. AMCFGR_EL0 is applicable to both the architected and the auxiliary counter groups. AMU AMCFGR_EL0 is a 64-bit register. 63 32 63:32 Reserved, RES0. NCG 31 28 31:28 Defines the number of counter groups implemented, minus one. All other values are reserved. 0b0000 One counter group implemented. 0b0001 Two counter groups implemented. RO 27 25 27:25 Reserved, RES0. HDBG 24 24 24 Halt-on-debug supported. This feature must be supported, and so this bit is 1. 0b0 AMCR_EL0.HDBG is RES0. 0b1 AMCR_EL0.HDBG is read/write. RO 23 14 23:14 Reserved, RAZ. SIZE 13 8 13:8 Defines the size of the activity monitor event counters, minus one. The counters are 64-bit, so the value of this field is 0b111111. This field is used by software to determine the spacing of the counters in the memory-map. The counters are at doubleword-aligned addresses. Reads as 0b111111. RO N 7 0 7:0 Defines the number of activity monitor event counters implemented in all groups. One less than the sum of AMCGCR_EL0.CG1NC and AMCGCR_EL0.CG0NC. This field has an IMPLEMENTATION DEFINED value. RO MRS <Xt>, AMCFGR_EL0 if !IsFeatureImplemented(FEAT_AMUv1) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TAM == '1' then Undefined(); elsif AMUSERENR_EL0().EN == '0' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && CPTR_EL2().TAM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMCFGR_EL0(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TAM == '1' then Undefined(); elsif EL2Enabled() && CPTR_EL2().TAM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMCFGR_EL0(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TAM == '1' then Undefined(); elsif HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMCFGR_EL0(); end; elsif PSTATE.EL == EL3 then X{64}(t) = AMCFGR_EL0(); end; 2026-03-26 20:27:25 2026-03_rel