<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<?xml-stylesheet href="one_register.xsl" type="text/xsl" ?>







<register_page>
  <registers>
  
    <register execution_state="AArch64" is_register="True" is_internal="True" is_stub_entry="False">
      <reg_short_name>AMCG1IDR_EL0</reg_short_name>
        
        <reg_long_name>Activity Monitors Counter Group 1 Identification Register</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when FEAT_AMUv1p1 is implemented</reg_condition>
      




          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Defines which auxiliary counters are implemented, and which of them have a corresponding virtual offset register, <register_link state="AArch64" id="AArch64-amevcntvoff1n_el2.xml">AMEVCNTVOFF1&lt;n&gt;_EL2</register_link> implemented.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>AMU</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>AMCG1IDR_EL0 is a 64-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="64">
  <text_before_fields/>
  <field id="fieldset_0-63_32" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>63</field_msb>
    <field_lsb>32</field_lsb>
    <rel_range>63:32</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-31_16" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>AMEVCNTOFF1&lt;n&gt;_EL2</field_name>
    <field_msb>31</field_msb>
    <field_lsb>16</field_lsb>
    <rel_range>31:16</rel_range>
    <field_description order="before">
      <para>Indicates which implemented auxiliary counters have a corresponding virtual offset register, <register_link state="AArch64" id="AArch64-amevcntvoff1n_el2.xml">AMEVCNTVOFF1&lt;n&gt;_EL2</register_link> implemented.</para>
    </field_description>
    <field_array_indexes index_variable="n" element_size="1" range_specifier="n+16">
      <field_array_index>
        <field_array_start>15</field_array_start>
        <field_array_end>0</field_array_end>
      </field_array_index>
    </field_array_indexes>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description>
          <para><register_link state="AArch64" id="AArch64-amevcntr1n_el0.xml">AMEVCNTR1&lt;n&gt;_EL0</register_link> does not have an offset, or is not implemented.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description>
          <para>The offset <register_link state="AArch64" id="AArch64-amevcntvoff1n_el2.xml">AMEVCNTVOFF1&lt;n&gt;_EL2</register_link> is implemented for <register_link state="AArch64" id="AArch64-amevcntr1n_el0.xml">AMEVCNTR1&lt;n&gt;_EL0</register_link>.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
  </field>
  <field id="fieldset_0-15_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>AMEVCNTR1&lt;n&gt;_EL0</field_name>
    <field_msb>15</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>15:0</rel_range>
    <field_description order="before">
      <para>Indicates which auxiliary counters <register_link state="AArch64" id="AArch64-amevcntr1n_el0.xml">AMEVCNTR1&lt;n&gt;_EL0</register_link> are implemented.</para>
    </field_description>
    <field_array_indexes index_variable="n" element_size="1" range_specifier="n">
      <field_array_index>
        <field_array_start>15</field_array_start>
        <field_array_end>0</field_array_end>
      </field_array_index>
    </field_array_indexes>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description>
          <para><register_link state="AArch64" id="AArch64-amevcntr1n_el0.xml">AMEVCNTR1&lt;n&gt;_EL0</register_link> is not implemented.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description>
          <para><register_link state="AArch64" id="AArch64-amevcntr1n_el0.xml">AMEVCNTR1&lt;n&gt;_EL0</register_link> is implemented.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="64">
  <fieldat id="fieldset_0-63_32" msb="63" lsb="32"/>
  <fieldat id="fieldset_0-31_16" label="AMEVCNTOFF115_EL2" msb="31" lsb="31"/>
  <fieldat id="fieldset_0-31_16" label="AMEVCNTOFF114_EL2" msb="30" lsb="30"/>
  <fieldat id="fieldset_0-31_16" label="AMEVCNTOFF113_EL2" msb="29" lsb="29"/>
  <fieldat id="fieldset_0-31_16" label="AMEVCNTOFF112_EL2" msb="28" lsb="28"/>
  <fieldat id="fieldset_0-31_16" label="AMEVCNTOFF111_EL2" msb="27" lsb="27"/>
  <fieldat id="fieldset_0-31_16" label="AMEVCNTOFF110_EL2" msb="26" lsb="26"/>
  <fieldat id="fieldset_0-31_16" label="AMEVCNTOFF19_EL2" msb="25" lsb="25"/>
  <fieldat id="fieldset_0-31_16" label="AMEVCNTOFF18_EL2" msb="24" lsb="24"/>
  <fieldat id="fieldset_0-31_16" label="AMEVCNTOFF17_EL2" msb="23" lsb="23"/>
  <fieldat id="fieldset_0-31_16" label="AMEVCNTOFF16_EL2" msb="22" lsb="22"/>
  <fieldat id="fieldset_0-31_16" label="AMEVCNTOFF15_EL2" msb="21" lsb="21"/>
  <fieldat id="fieldset_0-31_16" label="AMEVCNTOFF14_EL2" msb="20" lsb="20"/>
  <fieldat id="fieldset_0-31_16" label="AMEVCNTOFF13_EL2" msb="19" lsb="19"/>
  <fieldat id="fieldset_0-31_16" label="AMEVCNTOFF12_EL2" msb="18" lsb="18"/>
  <fieldat id="fieldset_0-31_16" label="AMEVCNTOFF11_EL2" msb="17" lsb="17"/>
  <fieldat id="fieldset_0-31_16" label="AMEVCNTOFF10_EL2" msb="16" lsb="16"/>
  <fieldat id="fieldset_0-15_0" label="AMEVCNTR115_EL0" msb="15" lsb="15"/>
  <fieldat id="fieldset_0-15_0" label="AMEVCNTR114_EL0" msb="14" lsb="14"/>
  <fieldat id="fieldset_0-15_0" label="AMEVCNTR113_EL0" msb="13" lsb="13"/>
  <fieldat id="fieldset_0-15_0" label="AMEVCNTR112_EL0" msb="12" lsb="12"/>
  <fieldat id="fieldset_0-15_0" label="AMEVCNTR111_EL0" msb="11" lsb="11"/>
  <fieldat id="fieldset_0-15_0" label="AMEVCNTR110_EL0" msb="10" lsb="10"/>
  <fieldat id="fieldset_0-15_0" label="AMEVCNTR19_EL0" msb="9" lsb="9"/>
  <fieldat id="fieldset_0-15_0" label="AMEVCNTR18_EL0" msb="8" lsb="8"/>
  <fieldat id="fieldset_0-15_0" label="AMEVCNTR17_EL0" msb="7" lsb="7"/>
  <fieldat id="fieldset_0-15_0" label="AMEVCNTR16_EL0" msb="6" lsb="6"/>
  <fieldat id="fieldset_0-15_0" label="AMEVCNTR15_EL0" msb="5" lsb="5"/>
  <fieldat id="fieldset_0-15_0" label="AMEVCNTR14_EL0" msb="4" lsb="4"/>
  <fieldat id="fieldset_0-15_0" label="AMEVCNTR13_EL0" msb="3" lsb="3"/>
  <fieldat id="fieldset_0-15_0" label="AMEVCNTR12_EL0" msb="2" lsb="2"/>
  <fieldat id="fieldset_0-15_0" label="AMEVCNTR11_EL0" msb="1" lsb="1"/>
  <fieldat id="fieldset_0-15_0" label="AMEVCNTR10_EL0" msb="0" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          






    
        
        <access_mechanism accessor="MRS AMCG1IDR_EL0" type="SystemAccessor">
            <encoding>
            <access_instruction>MRS &lt;Xt&gt;, AMCG1IDR_EL0</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b011"/>
                
                <enc n="CRn" v="0b1101"/>
                
                <enc n="CRm" v="0b0010"/>
                
                <enc n="op2" v="0b110"/>
            </encoding>
            <access_permission>
                <ps name="MRS" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_AMUv1p1) then
    Undefined();
elsif PSTATE.EL == EL0 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; CPTR_EL3().TAM == '1' then
        Undefined();
    elsif AMUSERENR_EL0().EN == '0' then
        if EL2Enabled() &amp;&amp; HCR_EL2().TGE == '1' then
            AArch64_SystemAccessTrap(EL2, 0x18);
        else
            AArch64_SystemAccessTrap(EL1, 0x18);
        end;
    elsif EL2Enabled() &amp;&amp; CPTR_EL2().TAM == '1' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; CPTR_EL3().TAM == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        X{64}(t) = AMCG1IDR_EL0();
    end;
elsif PSTATE.EL == EL1 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; CPTR_EL3().TAM == '1' then
        Undefined();
    elsif EL2Enabled() &amp;&amp; CPTR_EL2().TAM == '1' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; CPTR_EL3().TAM == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        X{64}(t) = AMCG1IDR_EL0();
    end;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; CPTR_EL3().TAM == '1' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; CPTR_EL3().TAM == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        X{64}(t) = AMCG1IDR_EL0();
    end;
elsif PSTATE.EL == EL3 then
    X{64}(t) = AMCG1IDR_EL0();
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>