AMCNTENCLR1_EL0 Activity Monitors Count Enable Clear Register 1 when FEAT_AMUv1 is implemented AMCNTENCLR1 Architectural AArch32 31 0 31 0 31 0 31 0 AMCNTENCLR1 Architectural External 31 0 31 0 31 0 31 0 AMCNTENSET1 Architectural External 31 0 31 0 31 0 31 0 AMCNTENCLR Architectural External 31 0 63 32 31 0 63 32 Disable control bits for the auxiliary activity monitors event counters, AMEVCNTR1<n>_EL0. AMU AMCNTENCLR1_EL0 is a 64-bit register. 63 16 63:16 Reserved, RES0. P<n> 15 0 15:0 Activity monitor event counter disable bit for AMEVCNTR1<n>_EL0. Possible values of each bit are: 15 0 0b0 When read, means that AMEVCNTR1<n>_EL0 is disabled. When written, has no effect. 0b1 When read, means that AMEVCNTR1<n>_EL0 is enabled. When written, disables AMEVCNTR1<n>_EL0. 0x00000000 When n >= UInt(AMCGCR_EL0.CG1NC) RAZ/WI When !IsG1ActivityMonitorImplemented(n) RAZ/WI W1C If there are no auxiliary monitor event counters implemented, reads and writes of AMCNTENCLR1_EL0 are UNDEFINED. There are no implemented auxiliary activity monitor event counters when AMCFGR_EL0.NCG == 0b0000. MRS <Xt>, AMCNTENCLR1_EL0 if !IsFeatureImplemented(FEAT_AMUv1) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TAM == '1' then Undefined(); elsif AMUSERENR_EL0().EN == '0' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && CPTR_EL2().TAM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HAFGRTR_EL2().AMCNTEN1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMCNTENCLR1_EL0(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TAM == '1' then Undefined(); elsif EL2Enabled() && CPTR_EL2().TAM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HAFGRTR_EL2().AMCNTEN1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMCNTENCLR1_EL0(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TAM == '1' then Undefined(); elsif HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMCNTENCLR1_EL0(); end; elsif PSTATE.EL == EL3 then X{64}(t) = AMCNTENCLR1_EL0(); end; MSR AMCNTENCLR1_EL0, <Xt> if !IsFeatureImplemented(FEAT_AMUv1) then Undefined(); elsif IsHighestEL(PSTATE.EL) then AMCNTENCLR1_EL0() = X{64}(t); else Undefined(); end; 2026-03-26 20:27:25 2026-03_rel