AMCR_EL0 Activity Monitors Control Register when FEAT_AMUv1 is implemented AMCR Architectural AArch32 31 0 31 0 31 0 31 0 AMCR Architectural External 31 0 31 0 31 0 31 0 when FEAT_AMU_EXT32 is implemented AMCR Architectural External 63 0 63 0 63 0 63 0 when FEAT_AMU_EXT64 is implemented Global control register for the activity monitors implementation. AMCR_EL0 is applicable to both the architected and the auxiliary counter groups. AMU AMCR_EL0 is a 64-bit register. 63 18 63:18 Reserved, RES0. CG1RZ 17 17 0 Counter Group 1 Read Zero. Reads from the memory-mapped view are unaffected by this field. 0b0 System register reads of AMEVCNTR1<n>_EL0 return the event count at all implemented and enabled Exception levels. 0b1 If the current Exception level is the highest implemented Exception level, system register reads of AMEVCNTR1<n>_EL0 return the event count. Otherwise, reads of AMEVCNTR1<n>_EL0 return a zero value. AU When FEAT_AMUv1p1 is implemented 17 17 17 Reserved, RES0. Otherwise 16 11 16:11 Reserved, RES0. HDBG 10 10 10 This bit controls whether activity monitor counting is halted when the PE is halted in Debug state. 0b0 Activity monitors do not halt counting when the PE is halted in Debug state. 0b1 Activity monitors halt counting when the PE is halted in Debug state. AU 9 0 9:0 Reserved, RES0. MRS <Xt>, AMCR_EL0 if !IsFeatureImplemented(FEAT_AMUv1) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TAM == '1' then Undefined(); elsif AMUSERENR_EL0().EN == '0' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && CPTR_EL2().TAM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMCR_EL0(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TAM == '1' then Undefined(); elsif EL2Enabled() && CPTR_EL2().TAM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMCR_EL0(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TAM == '1' then Undefined(); elsif HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMCR_EL0(); end; elsif PSTATE.EL == EL3 then X{64}(t) = AMCR_EL0(); end; MSR AMCR_EL0, <Xt> if !IsFeatureImplemented(FEAT_AMUv1) then Undefined(); elsif IsHighestEL(PSTATE.EL) then AMCR_EL0() = X{64}(t); else Undefined(); end; 2026-03-26 20:27:25 2026-03_rel