AMEVCNTR0<n>_EL0 Activity Monitors Event Counter Registers 0 when FEAT_AMUv1 is implemented 0 3 AMEVCNTR0<n> Architectural AArch32 31 0 31 0 31 0 31 0 AMEVCNTR0<n> Architectural External 63 0 63 0 63 0 63 0 Provides access to the architected activity monitor event counters. AMU AMEVCNTR0<n>_EL0 is a 64-bit register. ACNT 63 0 63:0 Architected activity monitor event counter n. Value of architected activity monitor event counter n, where n is the number of this register and is a number from 0 to 3. If all of the following are true, reads of the AMEVCNTR0<n>_EL0 registers from EL0 or EL1 return (PCount<63:0> - AMEVCNTVOFF0<n>_EL2<63:0>), where PCount is the physical count returned when AMEVCNTR0<n>_EL0 is read from EL2 or EL3: FEAT_AMUv1p1 is implemented. HCR_EL2.AMVOFFEN and SCR_EL3.AMVOFFEN are 1. EL2 is implemented and enabled in the current Security state, and the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}. If the counter is enabled, writes to this register have UNPREDICTABLE results. 0x0000000000000000 If <n> is greater than or equal to the number of architected activity monitor event counters, reads and writes of AMEVCNTR0<n>_EL0 are UNDEFINED. AMCGCR_EL0.CG0NC identifies the number of architected activity monitor event counters. 0-3 MRS <Xt>, AMEVCNTR0<m>_EL0 let m:integer = UInt(CRm[0] :: op2[2:0]); if !IsFeatureImplemented(FEAT_AMUv1) then Undefined(); elsif m >= 4 then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TAM == '1' then Undefined(); elsif AMUSERENR_EL0().EN == '0' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && CPTR_EL2().TAM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HAFGRTR_EL2()[m + 1] == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMEVCNTR0_EL0(m); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TAM == '1' then Undefined(); elsif EL2Enabled() && CPTR_EL2().TAM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HAFGRTR_EL2()[m + 1] == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMEVCNTR0_EL0(m); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TAM == '1' then Undefined(); elsif HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMEVCNTR0_EL0(m); end; elsif PSTATE.EL == EL3 then X{64}(t) = AMEVCNTR0_EL0(m); end; 0-3 MSR AMEVCNTR0<m>_EL0, <Xt> let m:integer = UInt(CRm[0] :: op2[2:0]); if !IsFeatureImplemented(FEAT_AMUv1) then Undefined(); elsif m >= 4 then Undefined(); elsif IsHighestEL(PSTATE.EL) then AMEVCNTR0_EL0(m) = X{64}(t); else Undefined(); end; 2026-03-26 20:27:25 2026-03_rel