<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<register_page>
  <registers>
  
    <register execution_state="AArch64" is_register="False" is_internal="True" is_stub_entry="False">
      <reg_short_name>APAS</reg_short_name>
        
        <reg_long_name>Associate PA space</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when FEAT_RME_GPC3 is implemented and FEAT_AA64 is implemented</reg_condition>
      




          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Associate a location with a specified PA space, for locations that are protected by a memory-side PAS filter.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
            <reg_group>Root</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>APAS is a 64-bit System instruction.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="64">
  <text_before_fields/>
  <field id="fieldset_0-63_63" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>NS</field_name>
    <field_msb>63</field_msb>
    <field_lsb>63</field_lsb>
    <rel_range>63</rel_range>
    <field_description order="before"><para>Together with the NSE field, selects the target physical address space.</para>
<table><tgroup cols="3"><thead><row><entry>NSE</entry><entry>NS</entry><entry>Meaning</entry></row></thead><tbody><row><entry><binarynumber>0b0</binarynumber></entry><entry><binarynumber>0b0</binarynumber></entry><entry>When Secure state is implemented, Secure. Otherwise reserved.</entry></row><row><entry><binarynumber>0b0</binarynumber></entry><entry><binarynumber>0b1</binarynumber></entry><entry>Non-secure.</entry></row><row><entry><binarynumber>0b1</binarynumber></entry><entry><binarynumber>0b0</binarynumber></entry><entry>Root.</entry></row><row><entry><binarynumber>0b1</binarynumber></entry><entry><binarynumber>0b1</binarynumber></entry><entry>Realm.</entry></row></tbody></tgroup></table></field_description>
  </field>
  <field id="fieldset_0-62_62" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>NSE</field_name>
    <field_msb>62</field_msb>
    <field_lsb>62</field_lsb>
    <rel_range>62</rel_range>
    <field_description order="before"><para>Together with the NS field, selects the target physical address space.</para>
<para>For a description of the values derived by evaluating NS and NSE together, see APAS.NS.</para></field_description>
  </field>
  <field id="fieldset_0-61_56" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>61</field_msb>
    <field_lsb>56</field_lsb>
    <rel_range>61:56</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-55_6" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>PA</field_name>
    <field_msb>55</field_msb>
    <field_lsb>6</field_lsb>
    <rel_range>55:6</rel_range>
    <field_description order="before"><para>Bits [55:6] of the Physical Address.</para>
<para>Bits of Xt corresponding to physical address bits above the implemented physical address size indicated in <register_link state="AArch64" id="AArch64-id_aa64mmfr0_el1.xml">ID_AA64MMFR0_EL1</register_link>.PARange are <arm-defined-word>RES0</arm-defined-word>. For example, if 44 bits of PA space are implemented, then Xt[55:44] are <arm-defined-word>RES0</arm-defined-word>.</para></field_description>
  </field>
  <field id="fieldset_0-5_3" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>5</field_msb>
    <field_lsb>3</field_lsb>
    <rel_range>5:3</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-2_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>TargetAttributes</field_name>
    <field_msb>2</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>2:0</rel_range>
    <field_description order="before">
      <para>The Target Attributes field is encoded as follows:</para>
    </field_description>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b000</field_value>
        <field_value_description>
          <para>Default behavior applies.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b001..0b111</field_value>
        <field_value_description>
          <para><arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word>.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="64">
  <fieldat id="fieldset_0-63_63" msb="63" lsb="63"/>
  <fieldat id="fieldset_0-62_62" msb="62" lsb="62"/>
  <fieldat id="fieldset_0-61_56" msb="61" lsb="56"/>
  <fieldat id="fieldset_0-55_6" msb="55" lsb="6"/>
  <fieldat id="fieldset_0-5_3" msb="5" lsb="3"/>
  <fieldat id="fieldset_0-2_0" msb="2" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          


  
    
      <access_permission_text>
        <para>This instruction is not subject to any translation, permission checks, or granule protection checks.</para>

      </access_permission_text>
      <access_permission_text>
        <para>This system instruction is an alias of the SYS instruction.</para>
      </access_permission_text>





    
        
        <access_mechanism accessor="APAS" type="SystemAccessor">
            <encoding>
            <access_instruction>APAS &lt;Xt&gt;</access_instruction>
                
                <enc n="op0" v="0b01"/>
                
                <enc n="op1" v="0b110"/>
                
                <enc n="CRn" v="0b0111"/>
                
                <enc n="CRm" v="0b0000"/>
                
                <enc n="op2" v="0b000"/>
            </encoding>
            <access_permission>
                <ps name="APAS" sections="1" secttype="access_permission">
                <pstext>
if !(IsFeatureImplemented(FEAT_RME_GPC3) &amp;&amp; IsFeatureImplemented(FEAT_AA64)) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    Undefined();
elsif PSTATE.EL == EL2 then
    Undefined();
elsif PSTATE.EL == EL3 then
    AArch64_APAS(X{64}(t));
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>