AT S1E1W Address Translate Stage 1 EL1 Write when FEAT_AA64 is implemented Performs stage 1 address translation, with permissions as if writing to the given virtual address from EL1, or from EL2 if the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, using the following translation regime: When EL2 is implemented and enabled in the Security state described by the current Effective value of SCR_EL3.{NSE, NS}: If the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, the EL1&0 translation regime, accessed from EL1. If the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, the EL2&0 translation regime, accessed from EL2. Otherwise, the EL1&0 translation regime, accessed from EL1. When FEAT_RME is implemented, if the Effective value of SCR_EL3.{NSE, NS} is a reserved value, this instruction is UNDEFINED at EL3. Address AT S1E1W is a 64-bit System instruction. IA Input address for translation 63 0 63:0 Input address for translation. The resulting address can be read from the PAR_EL1. If the address translation instructions are targeting a translation regime that is using AArch32, and so has a VA of only 32 bits, then VA[63:32] is RES0. This system instruction is an alias of the SYS instruction. AT S1E1W, <Xt> if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().AT == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().ATS1E1W == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_AT(X{64}(t), TranslationStage_1, EL1, ATAccess_Write); end; elsif PSTATE.EL == EL2 then AArch64_AT(X{64}(t), TranslationStage_1, EL1, ATAccess_Write); elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_RME) && EffectiveSCR_EL3_NS() == '0' && EffectiveSCR_EL3_NSE() == '1' then Undefined(); else AArch64_AT(X{64}(t), TranslationStage_1, EL1, ATAccess_Write); end; end; 2026-03-26 20:27:25 2026-03_rel