<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<register_page>
  <registers>
  
    <register execution_state="AArch64" is_register="True" is_internal="True" is_stub_entry="False">
      <reg_short_name>BRBIDR0_EL1</reg_short_name>
        
        <reg_long_name>Branch Record Buffer ID0 Register</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when FEAT_BRBE is implemented</reg_condition>
      




          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Indicates the features of the branch buffer unit.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>BRBE</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>BRBIDR0_EL1 is a 64-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="64">
  <text_before_fields/>
  <field id="fieldset_0-63_16" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>63</field_msb>
    <field_lsb>16</field_lsb>
    <rel_range>63:16</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-15_12" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="True" is_partial_field="False" is_conditional_field_name="False">
    <field_name>CC</field_name>
    <field_msb>15</field_msb>
    <field_lsb>12</field_lsb>
    <rel_range>15:12</rel_range>
    <field_description order="before">
      <para>Cycle counter support. Defined values are:</para>
    </field_description>
    <field_description order="after">
      <para>All other values are reserved.</para>
    </field_description>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0101</field_value>
        <field_value_description>
          <para>20-bit cycle counter implemented.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_access>
      <field_access_state>
        <field_access_type>RO</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <field id="fieldset_0-11_8" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="True" is_partial_field="False" is_conditional_field_name="False">
    <field_name>FORMAT</field_name>
    <field_msb>11</field_msb>
    <field_lsb>8</field_lsb>
    <rel_range>11:8</rel_range>
    <field_description order="before">
      <para>Data format of records of the Branch record buffer. Defined values are:</para>
    </field_description>
    <field_description order="after">
      <para>All other values are reserved.</para>
    </field_description>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0000</field_value>
        <field_value_description>
          <para>Format 0.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_access>
      <field_access_state>
        <field_access_type>RO</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <field id="fieldset_0-7_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="True" is_partial_field="False" is_conditional_field_name="False">
    <field_name>NUMREC</field_name>
    <field_msb>7</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>7:0</rel_range>
    <field_description order="before">
      <para>Number of records supported.</para>
    </field_description>
    <field_description order="after">
      <para>All other values are reserved.</para>
    </field_description>
    <field_values impdef="True">
      <field_value_instance>
        <field_value>0x08</field_value>
        <field_value_description>
          <para>8 branch records implemented.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0x10</field_value>
        <field_value_description>
          <para>16 branch records implemented.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0x20</field_value>
        <field_value_description>
          <para>32 branch records implemented.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0x40</field_value>
        <field_value_description>
          <para>64 branch records implemented.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_access>
      <field_access_state>
        <field_access_type>RO</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="64">
  <fieldat id="fieldset_0-63_16" msb="63" lsb="16"/>
  <fieldat id="fieldset_0-15_12" msb="15" lsb="12"/>
  <fieldat id="fieldset_0-11_8" msb="11" lsb="8"/>
  <fieldat id="fieldset_0-7_0" msb="7" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          






    
        
        <access_mechanism accessor="MRS BRBIDR0_EL1" type="SystemAccessor">
            <encoding>
            <access_instruction>MRS &lt;Xt&gt;, BRBIDR0_EL1</access_instruction>
                
                <enc n="op0" v="0b10"/>
                
                <enc n="op1" v="0b001"/>
                
                <enc n="CRn" v="0b1001"/>
                
                <enc n="CRm" v="0b0010"/>
                
                <enc n="op2" v="0b000"/>
            </encoding>
            <access_permission>
                <ps name="MRS" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_BRBE) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; MDCR_EL3().SBRBE != '11' &amp;&amp; SCR_EL3().NS == '0' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; MDCR_EL3().SBRBE IN {'x0'} &amp;&amp; SCR_EL3().NS == '1' then
        Undefined();
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT) &amp;&amp; (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') &amp;&amp; HDFGRTR_EL2().nBRBIDR == '0' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3().SBRBE != '11' &amp;&amp; SCR_EL3().NS == '0' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3().SBRBE IN {'x0'} &amp;&amp; SCR_EL3().NS == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        X{64}(t) = BRBIDR0_EL1();
    end;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; MDCR_EL3().SBRBE != '11' &amp;&amp; SCR_EL3().NS == '0' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; MDCR_EL3().SBRBE IN {'x0'} &amp;&amp; SCR_EL3().NS == '1' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3().SBRBE != '11' &amp;&amp; SCR_EL3().NS == '0' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3().SBRBE IN {'x0'} &amp;&amp; SCR_EL3().NS == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        X{64}(t) = BRBIDR0_EL1();
    end;
elsif PSTATE.EL == EL3 then
    X{64}(t) = BRBIDR0_EL1();
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>