BRBINF<n>_EL1 Branch Record Buffer Information Register <n> when FEAT_BRBE is implemented 0 31 The information for Branch record n + (BRBFCR_EL1.BANK × 32). BRBE BRBINF<n>_EL1 is a 64-bit register. 63 47 63:47 Reserved, RES0. CCU 46 46 46 The number of PE clock cycles since the last Branch record entry is UNKNOWN. The value in this field is only valid when BRBINF<n>_EL1.VALID != 0b00. 0b0 Indicates that the number of PE clock cycles since the last Branch record is indicated by BRBINF<n>_EL1.CC. 0b1 Indicates that the number of PE clock cycles since the last Branch record is UNKNOWN. AU When BRBINF<n>_EL1.VALID == '00' RES0 RO CC 45 32 45:32 The number of PE clock cycles since the last Branch record entry. The format of this field uses a mantissa and exponent to express the cycle count value, as follows: CC bits[7:0] indicate the mantissa M. CC bits[13:8] indicate the exponent E. The cycle count is expressed using the following function: if IsZero(E), then UInt(M) else UInt('1':M:Zeros(UInt(E)-1)) If required, the cycle count is rounded to a multiple of 2^(E-1) towards zero before being encoded. A value of all ones in both the mantissa and exponent indicates the cycle count value exceeded the size of the cycle counter. The value in this field is only valid when BRBINF<n>_EL1.VALID != 0b00. AU BRBINF<n>_EL1.CCU == '1' BRBINF<n>_EL1.VALID == '00' RES0 RO 31 14 31:14 Reserved, RES0. TYPE 13 8 13:8 Branch type. All other values are reserved. The value in this field is only valid when BRBINF<n>_EL1.VALID != 0b00. 0b000000 Unconditional direct branch, excluding Branch with link. 0b000001 Indirect branch, excluding Branch with link, Return from subroutine, and Exception return. 0b000010 Direct Branch with link. 0b000011 Indirect Branch with link. 0b000101 Return from subroutine. 0b000111 Exception return. 0b001000 Conditional direct branch. 0b100001 Debug halt. 0b100010 Call. 0b100011 Trap. 0b100100 SError. 0b100110 Instruction debug. 0b100111 Data debug. 0b101010 Alignment. 0b101011 Inst Fault. 0b101100 Data Fault. 0b101110 IRQ. 0b101111 FIQ. 0b110000 IMPLEMENTATION DEFINED exception to EL3. 0b111001 Debug State Exit. AU When BRBINF<n>_EL1.VALID == '00' RES0 RO EL 7 6 7:6 The Exception level at the target address. The value in this field is only valid when BRBINF<n>_EL1.VALID == 0b11 or BRBINF<n>_EL1.VALID == 0b01. 0b00 EL0. 0b01 EL1. 0b10 EL2. 0b11 EL3. When FEAT_BRBEv1p1 is implemented AU BRBINF<n>_EL1.VALID == '00' BRBINF<n>_EL1.VALID == '10' RES0 RO MPRED 5 5 5 Branch mispredict. The value in this field is only valid when BRBINF<n>_EL1.VALID == 0b11 or BRBINF<n>_EL1.VALID == 0b10. 0b0 Branch was correctly predicted or the result of the prediction was not captured. 0b1 Branch was incorrectly predicted. AU BRBINF<n>_EL1.VALID == '00' BRBINF<n>_EL1.VALID == '01' BRBINF<n>_EL1.TYPE[5] == '1' RES0 RO 4 2 4:2 Reserved, RES0. VALID 1 0 1:0 The Branch record is valid. 0b00 This Branch record is not valid. The values of following fields are not valid: BRBTGT<n>_EL1.ADDRESS. BRBSRC<n>_EL1.ADDRESS. BRBINF<n>_EL1.MPRED. BRBINF<n>_EL1.LASTFAILED. BRBINF<n>_EL1.T. BRBINF<n>_EL1.EL. BRBINF<n>_EL1.TYPE. BRBINF<n>_EL1.CC. BRBINF<n>_EL1.CCU. 0b01 This Branch record is valid. The values of following fields are not valid: BRBSRC<n>_EL1.ADDRESS. BRBINF<n>_EL1.T. BRBINF<n>_EL1.MPRED. 0b10 This Branch record is valid. The values of following fields are not valid: BRBTGT<n>_EL1.ADDRESS. BRBINF<n>_EL1.EL. 0b11 This Branch record is valid. AU BRBINF<n>_EL1 reads-as-zero if n + (BRBFCR_EL1.BANK × 32) >= BRBIDR0_EL1.NUMREC. 0-31 MRS <Xt>, BRBINF<m>_EL1 let m:integer = UInt(op2[2] :: CRm[3:0]); if !IsFeatureImplemented(FEAT_BRBE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().nBRBDATA == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif m + (UInt(BRBFCR_EL1().BANK) * 32) >= NUM_BRBE_RECORDS then X{64}(t) = Zeros{64}; else X{64}(t) = BRBINF_EL1(m); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif m + (UInt(BRBFCR_EL1().BANK) * 32) >= NUM_BRBE_RECORDS then X{64}(t) = Zeros{64}; else X{64}(t) = BRBINF_EL1(m); end; elsif PSTATE.EL == EL3 then if m + (UInt(BRBFCR_EL1().BANK) * 32) >= NUM_BRBE_RECORDS then X{64}(t) = Zeros{64}; else X{64}(t) = BRBINF_EL1(m); end; end; 2026-03-26 20:27:25 2026-03_rel