BRBTGT<n>_EL1 Branch Record Buffer Target Address Register <n> when FEAT_BRBE is implemented 0 31 The target address of Branch record n + (BRBFCR_EL1.BANK × 32). BRBE BRBTGT<n>_EL1 is a 64-bit register. ADDRESS 63 0 63:0 Target virtual address of the Branch record. When an indirect write occurs with a value with ADDRESS bits [63:P] indicating an invalid address, an UNKNOWN value which indicates an invalid address is written to bits [63:P]. An invalid address is: For an address in a translation regime with 2 VA ranges, with bits [63:P] not all zeroes or all ones. For an address in a translation regime with a single VA range, with bits [63:P] not all zeroes. P is defined as: 56, when FEAT_LVA3 is implemented. 52, when FEAT_LVA is implemented. 48, otherwise. The value in bits [P-1:0] is the value written. When an indirect write occurs with a value with ADDRESS bits [63:P] indicating a valid address, the written value is written to bits [63:0], and a read of the register returns the written value. AU BRBINF<n>_EL1.VALID == '00' BRBINF<n>_EL1.VALID == '10' RES0 RO BRBTGT<n>_EL1 is RES0 if n + (BRBFCR_EL1.BANK × 32) >= BRBIDR0_EL1.NUMREC. 0-31 MRS <Xt>, BRBTGT<m>_EL1 let m:integer = UInt(op2[2] :: CRm[3:0]); if !IsFeatureImplemented(FEAT_BRBE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().nBRBDATA == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif m + (UInt(BRBFCR_EL1().BANK) * 32) >= NUM_BRBE_RECORDS then X{64}(t) = Zeros{64}; else X{64}(t) = BRBTGT_EL1(m); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif m + (UInt(BRBFCR_EL1().BANK) * 32) >= NUM_BRBE_RECORDS then X{64}(t) = Zeros{64}; else X{64}(t) = BRBTGT_EL1(m); end; elsif PSTATE.EL == EL3 then if m + (UInt(BRBFCR_EL1().BANK) * 32) >= NUM_BRBE_RECORDS then X{64}(t) = Zeros{64}; else X{64}(t) = BRBTGT_EL1(m); end; end; 2026-03-26 20:27:25 2026-03_rel