CCSIDR_EL1 Current Cache Size ID Register when FEAT_AA64 is implemented CCSIDR Architectural AArch32 31 0 31 0 31 0 31 0 CCSIDR2 Architectural AArch32 63 32 31 0 63 32 31 0 Provides information about the architecture of the currently selected cache. Identification Registers The implementation includes one CCSIDR_EL1 for each cache that it can access. CSSELR_EL1 selects which Cache Size ID Register is accessible. CCSIDR_EL1 is a 64-bit register. When FEAT_CCIDX is implemented IsFeatureImplemented(FEAT_CCIDX) The parameters NumSets, Associativity, and LineSize in these registers define the architecturally visible parameters that are required for the cache maintenance by Set/Way instructions. They are not guaranteed to represent the actual microarchitectural features of a design. You cannot make any inference about the actual sizes of caches based on these parameters. 63 56 63:56 Reserved, RES0. NumSets 55 32 55:32 (Number of sets in cache) - 1, therefore a value of 0 indicates 1 set in the cache. The number of sets does not have to be a power of 2. 31 24 31:24 Reserved, RES0. Associativity 23 3 23:3 (Associativity of cache) - 1, therefore a value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2. LineSize 2 0 2:0 (Log₂(Number of bytes in cache line)) - 4. For example: For a line length of 16 bytes: Log₂(16) = 4, LineSize entry = 0. This is the minimum line length. For a line length of 32 bytes: Log₂(32) = 5, LineSize entry = 1. The C++ 17 specification has two defined parameters relating to the granularity of memory that does not interfere. For generic software and tools, Arm will set the hardware_destructive_interference_size parameter to 256 bytes and the hardware_constructive_interference_size parameter to 64 bytes.When FEAT_MTE2 is implemented, where a cache only holds Allocation tags, this field is RES0. !IsFeatureImplemented(FEAT_CCIDX) The parameters NumSets, Associativity, and LineSize in these registers define the architecturally visible parameters that are required for the cache maintenance by Set/Way instructions. They are not guaranteed to represent the actual microarchitectural features of a design. You cannot make any inference about the actual sizes of caches based on these parameters. 63 32 63:32 Reserved, RES0. 31 28 31:28 Reserved, UNKNOWN. NumSets 27 13 27:13 (Number of sets in cache) - 1, therefore a value of 0 indicates 1 set in the cache. The number of sets does not have to be a power of 2. Associativity 12 3 12:3 (Associativity of cache) - 1, therefore a value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2. LineSize 2 0 2:0 (Log₂(Number of bytes in cache line)) - 4. For example: For a line length of 16 bytes: Log₂(16) = 4, LineSize entry = 0. This is the minimum line length. For a line length of 32 bytes: Log₂(32) = 5, LineSize entry = 1. When FEAT_MTE2 is implemented, where a cache only holds Allocation tags, this field is RES0. The C++ 17 specification has two defined parameters relating to the granularity of memory that does not interfere. For generic software and tools, Arm will set the hardware_destructive_interference_size parameter to 256 bytes and the hardware_constructive_interference_size parameter to 64 bytes. When FEAT_CCIDX is implemented If CSSELR_EL1.{TnD, Level, InD} is programmed to a cache level that is not implemented, then on a read of the CCSIDR_EL1 the behavior is CONSTRAINED UNPREDICTABLE, and can be one of the following: The CCSIDR_EL1 read is treated as NOP. The CCSIDR_EL1 read is UNDEFINED. If FEAT_IDST is implemented, this is permitted to be reported with EC syndrome value 0x18. The CCSIDR_EL1 read returns an UNKNOWN value. MRS <Xt>, CCSIDR_EL1 if !IsFeatureImplemented(FEAT_AA64) then UnimplementedIDRegister(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().TID2 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_EVT) && HCR_EL2().TID4 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().CCSIDR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else X{64}(t) = CCSIDR_EL1(); end; elsif PSTATE.EL == EL2 then X{64}(t) = CCSIDR_EL1(); elsif PSTATE.EL == EL3 then X{64}(t) = CCSIDR_EL1(); end; 2026-03-26 20:27:25 2026-03_rel