CNTHCTL_EL2 Counter-timer Hypervisor Control Register when FEAT_AA64 is implemented CNTHCTL Architectural AArch32 31 0 31 0 31 0 31 0 Controls the generation of an event stream from the physical counter, and access from EL1 to the physical counter and the EL1 physical timer. Virt If EL2 is not implemented, this register is RES0 from EL3. Fields that control the generation of events from the event stream have an effect regardless of the current Exception level and whether EL2 is enabled in the current Security state. All other fields have no effect if EL2 is not enabled in the current Security state. CNTHCTL_EL2 is a 64-bit register. When EffectiveHCR_EL2_E2H() == '1' EffectiveHCR_EL2_E2H() == '1' 63 20 63:20 Reserved, RES0. CNTPMASK 19 19 0 This bit is RES0 in Non-secure and Secure state. 0b0 This control has no effect on CNTP_CTL_EL0.IMASK. 0b1 CNTP_CTL_EL0.IMASK behaves as if set to 1 for all purposes other than a direct read of the field. AU When FEAT_RME is implemented 19 19 19 Reserved, RES0. Otherwise CNTVMASK 18 18 0 This bit is RES0 in Non-secure and Secure state. 0b0 This control has no effect on CNTV_CTL_EL0.IMASK. 0b1 CNTV_CTL_EL0.IMASK behaves as if set to 1 for all purposes other than a direct read of the field. AU When FEAT_RME is implemented 18 18 18 Reserved, RES0. Otherwise EVNTIS 17 17 0 Controls the scale of the generation of the event stream. This control applies regardless of the value of the CNTHCTL_EL2.ECV bit. 0b0 The CNTHCTL_EL2.EVNTI field applies to CNTPCT_EL0[15:0]. 0b1 The CNTHCTL_EL2.EVNTI field applies to CNTPCT_EL0[23:8]. AU When FEAT_ECV is implemented 17 17 17 Reserved, RES0. Otherwise EL1NVVCT 16 16 0 When HCR_EL2.TGE is 0 and the Effective value of HCR_EL2.{NV2, NV1, NV} is {1, 0, 1}, traps EL1 accesses to the specified EL1 virtual timer registers using the EL02 descriptors to EL2 as follows: Accesses to CNTV_CTL_EL02 and CNTV_CVAL_EL02 are trapped to EL2 and reported with EC syndrome value 0x18. If HCR_EL2.TGE is 1 or the Effective value of HCR_EL2.{NV2, NV1, NV} is not {1, 0, 1}, this control does not cause any instructions to be trapped. If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 0 other than for the purpose of a direct read. This control applies regardless of the value of the CNTHCTL_EL2.ECV bit. 0b0 This control does not cause any instructions to be trapped. 0b1 EL1 accesses to the specified registers are trapped to EL2. AU When FEAT_ECV is implemented 16 16 16 Reserved, RES0. Otherwise EL1NVPCT 15 15 0 When HCR_EL2.TGE is 0 and the Effective value of HCR_EL2.{NV2, NV1, NV} is {1, 0, 1}, traps EL1 accesses to the specified EL1 physical timer registers using the EL02 descriptors to EL2 as follows: Accesses to CNTP_CTL_EL02 and CNTP_CVAL_EL02 are trapped to EL2 and reported with EC syndrome value 0x18. If HCR_EL2.TGE is 1 or the Effective value of HCR_EL2.{NV2, NV1, NV} is not {1, 0, 1}, this control does not cause any instructions to be trapped. If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 0 other than for the purpose of a direct read. This control applies regardless of the value of the CNTHCTL_EL2.ECV bit. 0b0 This control does not cause any instructions to be trapped. 0b1 EL1 accesses to the specified registers are trapped to EL2. AU When FEAT_ECV is implemented 15 15 15 Reserved, RES0. Otherwise EL1TVCT 14 14 0 Traps EL0 and EL1 accesses to the EL1 virtual counter registers to EL2 when EL2 is enabled in the current Security state, as follows: In AArch64 state, accesses to CNTVCT_EL0 and CNTVCTSS_EL0 are trapped to EL2 and reported using EC syndrome value 0x18, unless they are trapped by CNTKCTL_EL1.EL0VCTEN. In AArch32 state, accesses to CNTVCT are trapped to EL2 and reported with EC syndrome value 0x04, unless they are trapped by CNTKCTL_EL1.EL0VCTEN or CNTKCTL.PL0VCTEN. If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 0 other than for the purpose of a direct read. If HCR_EL2.TGE is 1, this control does not cause any instructions to be trapped. This control applies regardless of the value of the CNTHCTL_EL2.ECV bit. 0b0 This control does not cause any instructions to be trapped. 0b1 EL0 and EL1 accesses to the specified registers are trapped to EL2. AU When FEAT_ECV is implemented 14 14 14 Reserved, RES0. Otherwise EL1TVT 13 13 0 When the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, traps EL0 and EL1 accesses to the EL1 virtual timer registers to EL2, when EL2 is enabled for the current Security state, as follows: In AArch64 state, accesses to the following registers are trapped to EL2 and reported with EC syndrome value 0x18, unless they are trapped by CNTKCTL_EL1.EL0VTEN: CNTV_CTL_EL0. CNTV_CVAL_EL0. CNTV_TVAL_EL0. In AArch32 state, MRC and MCR accesses to the following registers are trapped to EL2 and reported using EC syndrome value 0x03, and MCRR and MRRC accesses are trapped to EL2 and reported using EC syndrome value 0x04, unless they are trapped by CNTKCTL_EL1.EL0VTEN or CNTKCTL.PL0VTEN: CNTV_CTL. CNTV_CVAL. CNTV_TVAL. If HCR_EL2.TGE is 1, this control does not cause any instructions to be trapped. If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 0 other than for the purpose of a direct read. This control applies regardless of the value of the CNTHCTL_EL2.ECV bit. 0b0 This control does not cause any instructions to be trapped. 0b1 EL0 and EL1 accesses to the specified registers are trapped to EL2. AU When FEAT_ECV is implemented 13 13 13 Reserved, RES0. Otherwise ECV 12 12 0 Enables the Enhanced Counter Virtualization functionality registers. When the Enhanced Counter Virtualization is enabled, the behavior is as follows: An MRS to CNTPCT_EL0 from either EL0 or EL1 that is not trapped will return the value (PCount<63:0> - CNTPOFF_EL2<63:0>). The EL1 physical timer interrupt is triggered when ((PCount<63:0> - CNTPOFF_EL2<63:0>) - PCVal<63:0>) is greater than or equal to 0. PCount<63:0> is the physical count returned when CNTPCT_EL0 is read from EL2 or EL3. PCVal<63:0> is the EL1 physical timer compare value for this timer. When HCR_EL2.TGE is 1 or SCR_EL3.{NS, EEL2} is {0, 0}, the Effective value of this field is 0. 0b0 Enhanced Counter Virtualization functionality is disabled. 0b1 Enhanced Counter Virtualization functionality is enabled. AU When FEAT_ECV_POFF is implemented 12 12 12 Reserved, RES0. Otherwise EL1PTEN 11 11 11 When HCR_EL2.TGE is 0, traps EL0 and EL1 accesses to the EL1 physical timer registers to EL2 when EL2 is enabled in the current Security state, as follows: In AArch64 state, accesses to the following registers are trapped to EL2 and reported with EC syndrome value 0x18, unless they are trapped by CNTKCTL_EL1.EL0PTEN: CNTP_CTL_EL0. CNTP_CVAL_EL0. CNTP_TVAL_EL0. In AArch32 state, MRC and MCR accesses to the following registers are trapped and reported using EC syndrome value 0x03 and MRRC and MCRR accesses are trapped and reported using EC syndrome value 0x04, unless they are trapped by CNTKCTL_EL1.EL0PTEN or CNTKCTL.PL0PTEN: CNTP_CTL. CNTP_CVAL. CNTP_TVAL. When HCR_EL2.TGE is 1, this control does not cause any instructions to be trapped. 0b0 EL0 and EL1 accesses to the specified registers are trapped to EL2. 0b1 This control does not cause any instructions to be trapped. AU EL1PCTEN 10 10 10 When HCR_EL2.TGE is 0, traps EL0 and EL1 accesses to the EL1 physical counter registers to EL2 when EL2 is enabled in the current Security state, as follows: In AArch64 state, accesses to CNTPCT_EL0 and CNTPCTSS_EL0 are trapped to EL2 and reported with EC syndrome value 0x18, unless they are trapped by CNTKCTL_EL1.EL0PCTEN. In AArch32 state, MRRC or MCRR accesses to CNTPCT are trapped to EL2 and reported with EC syndrome value 0x04, unless they are trapped by CNTKCTL_EL1.EL0PCTEN or CNTKCTL.PL0PCTEN. When HCR_EL2.TGE is 1, this control does not cause any instructions to be trapped. 0b0 EL0 and EL1 accesses to the specified registers are trapped to EL2. 0b1 This control does not cause any instructions to be trapped. AU EL0PTEN 9 9 9 When HCR_EL2.TGE is 1, traps EL0 accesses to the physical timer registers to EL2, as follows: In AArch64 state, accesses to the following registers are trapped to EL2 and reported with EC syndrome value 0x18: CNTP_CTL_EL0. CNTP_CVAL_EL0. CNTP_TVAL_EL0. In AArch32 state, MRC and MCR accesses to the following registers are trapped and reported using EC syndrome value 0x03 and MRRC and MCRR accesses are trapped and reported using EC syndrome value 0x04: CNTP_CTL. CNTP_CVAL. CNTP_TVAL. When HCR_EL2.TGE is 0, this control does not cause any instructions to be trapped. 0b0 EL0 accesses to the specified registers are trapped to EL2. 0b1 This control does not cause any instructions to be trapped. AU EL0VTEN 8 8 8 When HCR_EL2.TGE is 1, traps EL0 accesses to the virtual timer registers to EL2 as follows: In AArch64 state, accesses to the following registers are trapped to EL2 and reported with EC syndrome value 0x18: CNTV_CTL_EL0. CNTV_CVAL_EL0. CNTV_TVAL_EL0. In AArch32 state, MRC and MCR accesses to the following registers are trapped and reported using EC syndrome value 0x03 and MRRC and MCRR accesses are trapped and reported using EC syndrome value 0x04: CNTV_CTL. CNTV_CVAL. CNTV_TVAL. When HCR_EL2.TGE is 0, this control does not cause any instructions to be trapped. 0b0 EL0 accesses to the specified registers are trapped to EL2. 0b1 This control does not cause any instructions to be trapped. AU EVNTI 7 4 7:4 Selects which bit of CNTPCT_EL0, as seen from EL2, is the trigger for the event stream generated from that counter when that stream is enabled. If FEAT_ECV is implemented, and CNTHCTL_EL2.EVNTIS is 1, this field selects a trigger bit in the range 8 to 23 of CNTPCT_EL0. Otherwise, this field selects a trigger bit in the range 0 to 15 of CNTPCT_EL0. AU EVNTDIR 3 3 3 Controls which transition of the CNTPCT_EL0 trigger bit, as seen from EL2 and defined by EVNTI, generates an event when the event stream is enabled. 0b0 A 0 to 1 transition of the trigger bit triggers an event. 0b1 A 1 to 0 transition of the trigger bit triggers an event. AU EVNTEN 2 2 2 Enables the generation of an event stream from CNTPCT_EL0 as seen from EL2. 0b0 Disables the event stream. 0b1 Enables the event stream. AU EL0VCTEN 1 1 1 When HCR_EL2.TGE is 1, traps EL0 accesses to the frequency register and virtual counter registers to EL2, as follows: In AArch64 state, accesses to the following registers are trapped to EL2 and reported with EC syndrome value 0x18: CNTVCT_EL0. CNTVCTSS_EL0. CNTFRQ_EL0 if CNTHCTL_EL2.EL0PCTEN is 0. In AArch32 state, MRC and MCR accesses to the following registers are trapped and reported using EC syndrome value 0x03 and MRRC and MCRR accesses are trapped and reported using EC syndrome value 0x04: CNTVCT and if CNTHCTL.EL0PCTEN is 0, CNTFRQ. If HCR_EL2.TGE is 0, the field is ignored for all purposes other than direct reads and writes of the register. 0b0 EL0 accesses to the specified registers are trapped to EL2. 0b1 This control does not cause any instructions to be trapped. AU EL0PCTEN 0 0 0 Traps EL0 accesses to the frequency register and physical counter registers to EL2, as follows: In AArch64 state, accesses to the following registers are trapped to EL2 and reported with EC syndrome value 0x18: CNTPCT_EL0. CNTPCTSS_EL0. CNTFRQ_EL0 if CNTHCTL_EL2.EL0VCTEN is 0. In AArch32 state, MRC and MCR accesses to the following registers are trapped and reported using EC syndrome value 0x03 and MRRC and MCRR accesses are trapped and reported using EC syndrome value 0x04: CNTPCT and if CNTHCTL_EL2.EL0VCTEN is 0, CNTFRQ. If HCR_EL2.TGE is 0, the control does not cause any instructions to be trapped for all purposes other than direct reads and writes of the register. 0b0 From AArch64 state: EL0 accesses to the specified registers are trapped to EL2. 0b1 This control does not cause any instructions to be trapped. AU EffectiveHCR_EL2_E2H() == '0' The following field descriptions apply in all Armv8.0 implementations. The descriptions also explain the behavior when EL3 is implemented and EL2 is not implemented. 63 20 63:20 Reserved, RES0. CNTPMASK 19 19 0 This bit is RES0 in Non-secure and Secure state. 0b0 This control has no effect on CNTP_CTL_EL0.IMASK. 0b1 CNTP_CTL_EL0.IMASK behaves as if set to 1 for all purposes other than a direct read of the field. AU When FEAT_RME is implemented 19 19 19 Reserved, RES0. Otherwise CNTVMASK 18 18 0 This bit is RES0 in Non-secure and Secure state. 0b0 This control has no effect on CNTV_CTL_EL0.IMASK. 0b1 CNTV_CTL_EL0.IMASK behaves as if set to 1 for all purposes other than a direct read of the field. AU When FEAT_RME is implemented 18 18 18 Reserved, RES0. Otherwise EVNTIS 17 17 0 Controls the scale of the generation of the event stream. This control applies regardless of the value of the CNTHCTL_EL2.ECV bit. 0b0 The CNTHCTL_EL2.EVNTI field applies to CNTPCT_EL0[15:0]. 0b1 The CNTHCTL_EL2.EVNTI field applies to CNTPCT_EL0[23:8]. AU When FEAT_ECV is implemented 17 17 17 Reserved, RES0. Otherwise EL1NVVCT 16 16 0 When the Effective value of HCR_EL2.{NV2, NV1, NV} is {1, 0, 1}, traps EL1 accesses to the specified EL1 virtual timer registers using the EL02 descriptors to EL2 as follows: Accesses to CNTV_CTL_EL02 and CNTV_CVAL_EL02 are trapped to EL2 and reported with EC syndrome value 0x18. If the Effective value of HCR_EL2.{NV2, NV1, NV} is not {1, 0, 1}, this control does not cause any instructions to be trapped. If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 0 other than for the purpose of a direct read. This control applies regardless of the value of the CNTHCTL_EL2.ECV bit. 0b0 This control does not cause any instructions to be trapped. 0b1 EL1 accesses to the specified registers are trapped to EL2. AU When FEAT_ECV is implemented 16 16 16 Reserved, RES0. Otherwise EL1NVPCT 15 15 0 When the Effective value of HCR_EL2.{NV2, NV1, NV} is {1, 0, 1}, traps EL1 accesses to the specified EL1 physical timer registers using the EL02 descriptors to EL2 as follows: Accesses to CNTP_CTL_EL02 and CNTP_CVAL_EL02 are trapped to EL2 and reported with EC syndrome value 0x18. If the Effective value of HCR_EL2.{NV2, NV1, NV} is not {1, 0, 1}, this control does not cause any instructions to be trapped. If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 0 other than for the purpose of a direct read. This control applies regardless of the value of the CNTHCTL_EL2.ECV bit. 0b0 This control does not cause any instructions to be trapped. 0b1 EL1 accesses to the specified registers are trapped to EL2. AU When FEAT_ECV is implemented 15 15 15 Reserved, RES0. Otherwise EL1TVCT 14 14 0 Traps EL0 and EL1 accesses to the EL1 virtual counter registers to EL2, when EL2 is enabled in the current Security state, as follows: In AArch64 state, accesses to CNTVCT_EL0 and CNTVCTSS_EL0 are trapped to EL2 and reported using EC syndrome value 0x18, unless they are trapped by CNTKCTL_EL1.EL0VCTEN. In AArch32 state, accesses to CNTVCT are trapped to EL2 and reported using EC syndrome value 0x04, unless they are trapped by CNTKCTL_EL1.EL0VCTEN or CNTKCTL.PL0VCTEN. If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 0 other than for the purpose of a direct read. This control applies regardless of the value of the CNTHCTL_EL2.ECV bit. 0b0 This control does not cause any instructions to be trapped. 0b1 EL0 and EL1 accesses to the specified registers are trapped to EL2. AU When FEAT_ECV is implemented 14 14 14 Reserved, RES0. Otherwise EL1TVT 13 13 0 If the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, then traps EL0 and EL1 accesses to the EL1 virtual timer registers to EL2, when EL2 is enabled for the current Security state, as follows: In AArch64 state, accesses to the following registers are trapped to EL2 and reported with EC syndrome value 0x18, unless they are trapped by CNTKCTL_EL1.EL0VTEN: CNTV_CTL_EL0. CNTV_CVAL_EL0. CNTV_TVAL_EL0. In AArch32 state, MRC and MCR accesses to the following registers are trapped and reported using EC syndrome value 0x03 and MRRC and MCRR accesses are trapped and reported using EC syndrome value 0x04, unless they are trapped by CNTKCTL_EL1.EL0VTEN or CNTKCTL.PL0VTEN: CNTV_CTL. CNTV_CVAL. CNTV_TVAL. If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 0 other than for the purpose of a direct read. This control applies regardless of the value of the CNTHCTL_EL2.ECV bit. 0b0 This control does not cause any instructions to be trapped. 0b1 EL0 and EL1 accesses to the specified registers are trapped to EL2. AU When FEAT_ECV is implemented 13 13 13 Reserved, RES0. Otherwise ECV 12 12 0 Enables the Enhanced Counter Virtualization functionality registers. When the Enhanced Counter Virtualization is enabled, the behavior is as follows: An MRS to CNTPCT_EL0 from either EL0 or EL1 that is not trapped will return the value (PCount<63:0> - CNTPOFF_EL2<63:0>). The EL1 physical timer interrupt is triggered when ((PCount<63:0> - CNTPOFF_EL2<63:0>) - PCVal<63:0>) is greater than or equal to 0. PCount is the physical count returned when CNTPCT_EL0 is read from EL2 or EL3. PCVal<63:0> is the EL1 physical timer compare value for this timer. When SCR_EL3.{NS, EEL2} is {0, 0} or if FEAT_ECV_POFF is not implemented, the Effective value of this field is 0. 0b0 Enhanced Counter Virtualization functionality is disabled. 0b1 Enhanced Counter Virtualization functionality is enabled. AU When FEAT_ECV_POFF is implemented 12 12 12 Reserved, RES0. Otherwise 11 8 11:8 Reserved, RES0. EVNTI 7 4 7:4 Selects which bit of CNTPCT_EL0, as seen from EL2,is the trigger for the event stream generated from that counter when that stream is enabled. If FEAT_ECV is implemented, and CNTHCTL_EL2.EVNTIS is 1, this field selects a trigger bit in the range 8 to 23 of CNTPCT_EL0. Otherwise, this field selects a trigger bit in the range 0 to 15 of CNTPCT_EL0. AU EVNTDIR 3 3 3 Controls which transition of the CNTPCT_EL0 trigger bit, as seen from EL2 and defined by EVNTI, generates an event when the event stream is enabled. 0b0 A 0 to 1 transition of the trigger bit triggers an event. 0b1 A 1 to 0 transition of the trigger bit triggers an event. AU EVNTEN 2 2 2 Enables the generation of an event stream from CNTPCT_EL0 as seen from EL2. 0b0 Disables the event stream. 0b1 Enables the event stream. AU EL1PCEN 1 1 1 Traps EL0 and EL1 accesses to the EL1 physical timer registers to EL2 when EL2 is enabled in the current Security state, as follows: In AArch64 state, accesses to CNTP_CTL_EL0, CNTP_CVAL_EL0, CNTP_TVAL_EL0 are trapped to EL2, reported using EC syndrome value 0x18, unless they are trapped by CNTKCTL_EL1.EL0PTEN. In AArch32 state, MRC or MCR accesses to the following registers are trapped to EL2 and reported using EC syndrome value 0x03, and MRRC and MCRR accesses are trapped to EL2, reported using EC syndrome value 0x04, unless they are trapped by CNTKCTL_EL1.EL0PTEN or CNTKCTL.PL0PTEN: CNTP_CTL, CNTP_CVAL, CNTP_TVAL. If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 1 other than for the purpose of a direct read. 0b0 EL0 and EL1 accesses to the specified registers are trapped to EL2. 0b1 This control does not cause any instructions to be trapped. AU EL1PCTEN 0 0 0 Traps EL0 and EL1 accesses to the EL1 physical counter registers to EL2 when EL2 is enabled in the current Security state, as follows: In AArch64 state, accesses to CNTPCT_EL0 and CNTPCTSS_EL0 are trapped to EL2 and reported using EC syndrome value 0x18, unless they are trapped by CNTKCTL_EL1.EL0PCTEN. In AArch32 state, MRRC or MCRR accesses to CNTPCT are trapped to EL2 and reported using EC syndrome value 0x04, unless they are trapped by CNTKCTL_EL1.EL0PCTEN or CNTKCTL.PL0PCTEN. If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 1 other than for the purpose of a direct read. 0b0 EL0 and EL1 accesses to the specified registers are trapped to EL2. 0b1 This control does not cause any instructions to be trapped. AU When EffectiveHCR_EL2_E2H() == '1' When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the accessor name CNTHCTL_EL2 or CNTKCTL_EL1 are not guaranteed to be ordered with respect to accesses using the other accessor name. MRS <Xt>, CNTHCTL_EL2 if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then X{64}(t) = CNTHCTL_EL2(); elsif PSTATE.EL == EL3 then X{64}(t) = CNTHCTL_EL2(); end; MSR CNTHCTL_EL2, <Xt> if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then CNTHCTL_EL2() = X{64}(t); elsif PSTATE.EL == EL3 then CNTHCTL_EL2() = X{64}(t); end; MRS <Xt>, CNTKCTL_EL1 When FEAT_VHE is implemented if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then X{64}(t) = CNTKCTL_EL1(); elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then X{64}(t) = CNTHCTL_EL2_VHE(CNTHCTL_EL2()); else X{64}(t) = CNTKCTL_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = CNTKCTL_EL1(); end; MSR CNTKCTL_EL1, <Xt> When FEAT_VHE is implemented if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then CNTKCTL_EL1() = X{64}(t); elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then CNTHCTL_EL2() = CNTHCTL_EL2_VHE(X{64}(t)); else CNTKCTL_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then CNTKCTL_EL1() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel