CNTHP_CTL_EL2 Counter-timer Hypervisor Physical Timer Control Register when (EL3 is implemented or (EL3 is not implemented, EL2 is implemented, and FEAT_SEL2 is not implemented)) and FEAT_AA64 is implemented CNTHP_CTL Architectural AArch32 31 0 31 0 31 0 31 0 Control register for the EL2 physical timer. Virt If EL2 is not implemented, this register is RES0 from EL3. CNTHP_CTL_EL2 is a 64-bit register. 63 3 63:3 Reserved, RES0. ISTATUS 2 2 2 The status of the timer. This bit indicates whether the timer condition is met: When the value of the ENABLE bit is 1, ISTATUS indicates whether the timer condition is met. ISTATUS takes no account of the value of the IMASK bit. If the value of ISTATUS is 1 and the value of IMASK is 0 then the timer interrupt is asserted. When the value of the ENABLE bit is 0, the ISTATUS field is UNKNOWN. 0b0 Timer condition is not met. 0b1 Timer condition is met. AU RO IMASK 1 1 1 Timer interrupt mask bit. Permitted values are: For more information, see the description of the ISTATUS bit. 0b0 Timer interrupt is not masked by the IMASK bit. 0b1 Timer interrupt is masked by the IMASK bit. AU ENABLE 0 0 0 Enables the timer. Permitted values are: Setting this bit to 0 disables the timer output signal, but the timer value accessible from CNTHP_TVAL_EL2 continues to count down. Disabling the output signal might be a power-saving option. 0b0 Timer disabled. 0b1 Timer enabled. AU When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the accessor name CNTHP_CTL_EL2 or CNTP_CTL_EL0 are not guaranteed to be ordered with respect to accesses using the other accessor name. MRS <Xt>, CNTHP_CTL_EL2 if !((HaveEL(EL3) || (!HaveEL(EL3) && HaveEL(EL2) && !IsFeatureImplemented(FEAT_SEL2))) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then X{64}(t) = CNTHP_CTL_EL2(); elsif PSTATE.EL == EL3 then X{64}(t) = CNTHP_CTL_EL2(); end; MSR CNTHP_CTL_EL2, <Xt> if !((HaveEL(EL3) || (!HaveEL(EL3) && HaveEL(EL2) && !IsFeatureImplemented(FEAT_SEL2))) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then CNTHP_CTL_EL2() = X{64}(t); elsif PSTATE.EL == EL3 then CNTHP_CTL_EL2() = X{64}(t); end; MRS <Xt>, CNTP_CTL_EL0 if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then if !ELIsInHost(EL0) && CNTKCTL_EL1().EL0PTEN == '0' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && !ELIsInHost(EL2) && CNTHCTL_EL2().EL1PCEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL2) && HCR_EL2().TGE == '0' && CNTHCTL_EL2().EL1PTEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && CNTHCTL_EL2().EL0PTEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then X{64}(t) = CNTHPS_CTL_EL2(); elsif ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure) then X{64}(t) = CNTHP_CTL_EL2(); else X{64}(t) = CNTP_CTL_EL0(); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELIsInHost(EL2) && CNTHCTL_EL2().EL1PCEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL2) && CNTHCTL_EL2().EL1PTEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x180); else X{64}(t) = CNTP_CTL_EL0(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then X{64}(t) = CNTHPS_CTL_EL2(); elsif ELIsInHost(EL2) && !IsCurrentSecurityState(SS_Secure) then X{64}(t) = CNTHP_CTL_EL2(); else X{64}(t) = CNTP_CTL_EL0(); end; elsif PSTATE.EL == EL3 then X{64}(t) = CNTP_CTL_EL0(); end; MSR CNTP_CTL_EL0, <Xt> if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then if !ELIsInHost(EL0) && CNTKCTL_EL1().EL0PTEN == '0' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && !ELIsInHost(EL2) && CNTHCTL_EL2().EL1PCEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL2) && HCR_EL2().TGE == '0' && CNTHCTL_EL2().EL1PTEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && CNTHCTL_EL2().EL0PTEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then CNTHPS_CTL_EL2() = X{64}(t); elsif ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure) then CNTHP_CTL_EL2() = X{64}(t); else CNTP_CTL_EL0() = X{64}(t); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELIsInHost(EL2) && CNTHCTL_EL2().EL1PCEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL2) && CNTHCTL_EL2().EL1PTEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x180) = X{64}(t); else CNTP_CTL_EL0() = X{64}(t); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then CNTHPS_CTL_EL2() = X{64}(t); elsif ELIsInHost(EL2) && !IsCurrentSecurityState(SS_Secure) then CNTHP_CTL_EL2() = X{64}(t); else CNTP_CTL_EL0() = X{64}(t); end; elsif PSTATE.EL == EL3 then CNTP_CTL_EL0() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel