<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<register_page>
  <registers>
  
    <register execution_state="AArch64" is_register="True" is_internal="True" is_stub_entry="False">
      <reg_short_name>CNTKCTL_EL1</reg_short_name>
        
        <reg_long_name>Counter-timer Kernel Control Register</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when FEAT_AA64 is implemented</reg_condition>
      




          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        



    
      
      <reg_mapping>
        
  

    

  

    <mapped_name filename="AArch32-cntkctl.xml">CNTKCTL</mapped_name>
  <mapped_type>Architectural</mapped_type>
      <mapped_execution_state>AArch32</mapped_execution_state>
    <mapped_from_startbit>31</mapped_from_startbit>
    <mapped_from_endbit>0</mapped_from_endbit>
    <mapped_to_startbit>31</mapped_to_startbit>
    <mapped_to_endbit>0</mapped_to_endbit>
    <mapped_from_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_from_rangeset>
    <mapped_to_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_to_rangeset>

      </reg_mapping>

      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>When the Effective value of <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.{E2H, TGE} is {1, 1}, this register does not cause any event stream from the virtual counter to be generated, and does not control access to the counters and timers. The access to counters and timers at EL0 is controlled by <register_link state="AArch64" id="AArch64-cnthctl_el2.xml">CNTHCTL_EL2</register_link>.</para>

      </purpose_text>
      <purpose_text>
        <para>When <xref linkend="#FEAT_VHE">FEAT_VHE</xref> is not implemented, or when the Effective value of <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.{E2H, TGE} is not {1, 1}, this register controls the generation of an event stream from the virtual counter, and access from EL0 to the physical counter, virtual counter, EL1 physical timers, and the virtual timer.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>Timer</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>CNTKCTL_EL1 is a 64-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="64">
  <text_before_fields/>
  <field id="fieldset_0-63_20" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>63</field_msb>
    <field_lsb>20</field_lsb>
    <rel_range>63:20</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-19_19-1" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" reserved_type="RES0">
    <field_name>CNTPMASK</field_name>
    <field_msb>19</field_msb>
    <field_lsb>19</field_lsb>
    <rel_range>0</rel_range>
    <field_description order="before">
      <para>Reserved for software use in nested virtualization.</para>
    </field_description>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
    <fields_condition>When FEAT_RME is implemented and FEAT_NV2p1 is implemented</fields_condition>
  </field>
  <field id="fieldset_0-19_19-2" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>19</field_msb>
    <field_lsb>19</field_lsb>
    <rel_range>19</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
    <fields_condition>Otherwise</fields_condition>
  </field>
  <field id="fieldset_0-18_18-1" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" reserved_type="RES0">
    <field_name>CNTVMASK</field_name>
    <field_msb>18</field_msb>
    <field_lsb>18</field_lsb>
    <rel_range>0</rel_range>
    <field_description order="before">
      <para>Reserved for software use in nested virtualization.</para>
    </field_description>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
    <fields_condition>When FEAT_RME is implemented and FEAT_NV2p1 is implemented</fields_condition>
  </field>
  <field id="fieldset_0-18_18-2" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>18</field_msb>
    <field_lsb>18</field_lsb>
    <rel_range>18</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
    <fields_condition>Otherwise</fields_condition>
  </field>
  <field id="fieldset_0-17_17-1" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" reserved_type="RES0">
    <field_name>EVNTIS</field_name>
    <field_msb>17</field_msb>
    <field_lsb>17</field_lsb>
    <rel_range>0</rel_range>
    <field_description order="before">
      <para>Controls the scale of the generation of the event stream.</para>
    </field_description>
    <field_description order="after">
      <para>This control applies regardless of the value of the <register_link state="AArch64" id="AArch64-cnthctl_el2.xml">CNTHCTL_EL2</register_link>.ECV bit.</para>
    </field_description>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description>
          <para>The CNTKCTL_EL1.EVNTI field applies to <register_link state="AArch64" id="AArch64-cntvct_el0.xml">CNTVCT_EL0</register_link>[15:0].</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description>
          <para>The CNTKCTL_EL1.EVNTI field applies to <register_link state="AArch64" id="AArch64-cntvct_el0.xml">CNTVCT_EL0</register_link>[23:8].</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
    <fields_condition>When FEAT_ECV is implemented</fields_condition>
  </field>
  <field id="fieldset_0-17_17-2" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>17</field_msb>
    <field_lsb>17</field_lsb>
    <rel_range>17</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
    <fields_condition>Otherwise</fields_condition>
  </field>
  <field id="fieldset_0-16_16-1" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" reserved_type="RES0">
    <field_name>EL1NVVCT</field_name>
    <field_msb>16</field_msb>
    <field_lsb>16</field_lsb>
    <rel_range>0</rel_range>
    <field_description order="before">
      <para>Reserved for software use in nested virtualization.</para>
    </field_description>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
    <fields_condition>When FEAT_ECV is implemented and FEAT_NV2p1 is implemented</fields_condition>
  </field>
  <field id="fieldset_0-16_16-2" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>16</field_msb>
    <field_lsb>16</field_lsb>
    <rel_range>16</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
    <fields_condition>Otherwise</fields_condition>
  </field>
  <field id="fieldset_0-15_15-1" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" reserved_type="RES0">
    <field_name>EL1NVPCT</field_name>
    <field_msb>15</field_msb>
    <field_lsb>15</field_lsb>
    <rel_range>0</rel_range>
    <field_description order="before">
      <para>Reserved for software use in nested virtualization.</para>
    </field_description>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
    <fields_condition>When FEAT_ECV is implemented and FEAT_NV2p1 is implemented</fields_condition>
  </field>
  <field id="fieldset_0-15_15-2" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>15</field_msb>
    <field_lsb>15</field_lsb>
    <rel_range>15</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
    <fields_condition>Otherwise</fields_condition>
  </field>
  <field id="fieldset_0-14_14-1" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" reserved_type="RES0">
    <field_name>EL1TVCT</field_name>
    <field_msb>14</field_msb>
    <field_lsb>14</field_lsb>
    <rel_range>0</rel_range>
    <field_description order="before">
      <para>Reserved for software use in nested virtualization.</para>
    </field_description>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
    <fields_condition>When FEAT_ECV is implemented and FEAT_NV2p1 is implemented</fields_condition>
  </field>
  <field id="fieldset_0-14_14-2" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>14</field_msb>
    <field_lsb>14</field_lsb>
    <rel_range>14</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
    <fields_condition>Otherwise</fields_condition>
  </field>
  <field id="fieldset_0-13_13-1" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" reserved_type="RES0">
    <field_name>EL1TVT</field_name>
    <field_msb>13</field_msb>
    <field_lsb>13</field_lsb>
    <rel_range>0</rel_range>
    <field_description order="before">
      <para>Reserved for software use in nested virtualization.</para>
    </field_description>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
    <fields_condition>When FEAT_ECV is implemented and FEAT_NV2p1 is implemented</fields_condition>
  </field>
  <field id="fieldset_0-13_13-2" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>13</field_msb>
    <field_lsb>13</field_lsb>
    <rel_range>13</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
    <fields_condition>Otherwise</fields_condition>
  </field>
  <field id="fieldset_0-12_12-1" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" reserved_type="RES0">
    <field_name>ECV</field_name>
    <field_msb>12</field_msb>
    <field_lsb>12</field_lsb>
    <rel_range>0</rel_range>
    <field_description order="before">
      <para>Reserved for software use in nested virtualization.</para>
    </field_description>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
    <fields_condition>When FEAT_ECV is implemented and FEAT_NV2p1 is implemented</fields_condition>
  </field>
  <field id="fieldset_0-12_12-2" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>12</field_msb>
    <field_lsb>12</field_lsb>
    <rel_range>12</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
    <fields_condition>Otherwise</fields_condition>
  </field>
  <field id="fieldset_0-11_11-1" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" reserved_type="RES0">
    <field_name>EL1PTEN</field_name>
    <field_msb>11</field_msb>
    <field_lsb>11</field_lsb>
    <rel_range>0</rel_range>
    <field_description order="before">
      <para>Reserved for software use in nested virtualization.</para>
    </field_description>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
    <fields_condition>When FEAT_NV2p1 is implemented</fields_condition>
  </field>
  <field id="fieldset_0-11_11-2" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>11</field_msb>
    <field_lsb>11</field_lsb>
    <rel_range>11</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
    <fields_condition>Otherwise</fields_condition>
  </field>
  <field id="fieldset_0-10_10-1" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" reserved_type="RES0">
    <field_name>EL1PCTEN</field_name>
    <field_msb>10</field_msb>
    <field_lsb>10</field_lsb>
    <rel_range>0</rel_range>
    <field_description order="before">
      <para>Reserved for software use in nested virtualization.</para>
    </field_description>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
    <fields_condition>When FEAT_NV2p1 is implemented</fields_condition>
  </field>
  <field id="fieldset_0-10_10-2" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>10</field_msb>
    <field_lsb>10</field_lsb>
    <rel_range>10</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
    <fields_condition>Otherwise</fields_condition>
  </field>
  <field id="fieldset_0-9_9" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>EL0PTEN</field_name>
    <field_msb>9</field_msb>
    <field_lsb>9</field_lsb>
    <rel_range>9</rel_range>
    <field_description order="before"><para>Traps EL0 accesses to the physical timer registers to EL1, or to EL2 when it is implemented and enabled for the current Security state and <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.TGE is 1, as follows:</para>
<list type="unordered">
<listitem><content>In AArch64 state, the following registers are trapped and reported using EC syndrome value <hexnumber>0x18</hexnumber>:<list type="unordered">
<listitem><content><register_link state="AArch64" id="AArch64-cntp_ctl_el0.xml">CNTP_CTL_EL0</register_link>, <register_link state="AArch64" id="AArch64-cntp_cval_el0.xml">CNTP_CVAL_EL0</register_link>, and <register_link state="AArch64" id="AArch64-cntp_tval_el0.xml">CNTP_TVAL_EL0</register_link>.</content>
</listitem></list>
</content>
</listitem><listitem><content>In AArch32 state, MRC and MCR accesses to the following registers are trapped and reported using EC syndrome value <hexnumber>0x03</hexnumber>, MRRC and MCRR accesses are trapped and reported using EC syndrome value <hexnumber>0x04</hexnumber>:<list type="unordered">
<listitem><content><register_link state="AArch32" id="AArch32-cntp_ctl.xml">CNTP_CTL</register_link>, <register_link state="AArch32" id="AArch32-cntp_cval.xml">CNTP_CVAL</register_link>, <register_link state="AArch32" id="AArch32-cntp_tval.xml">CNTP_TVAL</register_link>.</content>
</listitem></list>
</content>
</listitem></list></field_description>
    <field_description order="after">
      <para>When the Effective value of <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.{E2H, TGE} is {1, 1}, this control does not cause any instructions to be trapped.</para>
    </field_description>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description>
          <para>EL0 accesses to the physical timer registers are trapped to EL1.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description>
          <para>This control does not cause any instructions to be trapped.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
  </field>
  <field id="fieldset_0-8_8" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>EL0VTEN</field_name>
    <field_msb>8</field_msb>
    <field_lsb>8</field_lsb>
    <rel_range>8</rel_range>
    <field_description order="before"><para>Traps EL0 accesses to the virtual timer registers to EL1, or to EL2 when it is implemented and enabled for the current Security state and <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.TGE is 1, as follows:</para>
<list type="unordered">
<listitem><content>In AArch64 state, accesses to the following registers are trapped and reported using EC syndrome value <hexnumber>0x18</hexnumber>:<list type="unordered">
<listitem><content><register_link state="AArch64" id="AArch64-cntv_ctl_el0.xml">CNTV_CTL_EL0</register_link>, <register_link state="AArch64" id="AArch64-cntv_cval_el0.xml">CNTV_CVAL_EL0</register_link>, and <register_link state="AArch64" id="AArch64-cntv_tval_el0.xml">CNTV_TVAL_EL0</register_link>.</content>
</listitem></list>
</content>
</listitem><listitem><content>In AArch32 state, MRC and MCR accesses to the following registers are trapped and reported using EC syndrome value <hexnumber>0x03</hexnumber>, MRRC and MCRR accesses are trapped using EC syndrome value <hexnumber>0x04</hexnumber>:<list type="unordered">
<listitem><content><register_link state="AArch32" id="AArch32-cntv_ctl.xml">CNTV_CTL</register_link>, <register_link state="AArch32" id="AArch32-cntv_cval.xml">CNTV_CVAL</register_link>, and <register_link state="AArch32" id="AArch32-cntv_tval.xml">CNTV_TVAL</register_link>.</content>
</listitem></list>
</content>
</listitem></list></field_description>
    <field_description order="after">
      <para>When the Effective value of <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.{E2H, TGE} is {1, 1}, this control does not cause any instructions to be trapped.</para>
    </field_description>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description>
          <para>EL0 accesses to the virtual timer registers are trapped.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description>
          <para>This control does not cause any instructions to be trapped.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
  </field>
  <field id="fieldset_0-7_4" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>EVNTI</field_name>
    <field_msb>7</field_msb>
    <field_lsb>4</field_lsb>
    <rel_range>7:4</rel_range>
    <field_description order="before"><para>Selects which bit of <register_link state="AArch64" id="AArch64-cntvct_el0.xml">CNTVCT_EL0</register_link>, as seen from EL1, is the trigger for the event stream generated from that counter when that stream is enabled.</para>
<para>If <xref linkend="#FEAT_ECV">FEAT_ECV</xref> is implemented, and CNTKCTL_EL1.EVNTIS is 1, this field selects a trigger bit in the range 8 to 23 of <register_link state="AArch64" id="AArch64-cntvct_el0.xml">CNTVCT_EL0</register_link>.</para>
<para>Otherwise, this field selects a trigger bit in the range 0 to 15 of <register_link state="AArch64" id="AArch64-cntvct_el0.xml">CNTVCT_EL0</register_link>.</para></field_description>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
  </field>
  <field id="fieldset_0-3_3" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>EVNTDIR</field_name>
    <field_msb>3</field_msb>
    <field_lsb>3</field_lsb>
    <rel_range>3</rel_range>
    <field_description order="before">
      <para>Controls which transition of the <register_link state="AArch64" id="AArch64-cntvct_el0.xml">CNTVCT_EL0</register_link> trigger bit, as seen from EL1 and defined by EVNTI, generates an event when the event stream is enabled.</para>
    </field_description>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description>
          <para>A 0 to 1 transition of the trigger bit triggers an event.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description>
          <para>A 1 to 0 transition of the trigger bit triggers an event.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
  </field>
  <field id="fieldset_0-2_2" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>EVNTEN</field_name>
    <field_msb>2</field_msb>
    <field_lsb>2</field_lsb>
    <rel_range>2</rel_range>
    <field_description order="before">
      <para>When <xref linkend="#FEAT_VHE">FEAT_VHE</xref> is not implemented, or the Effective value of <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.{E2H, TGE} is not {1, 1}, enables the generation of an event stream from <register_link state="AArch64" id="AArch64-cntvct_el0.xml">CNTVCT_EL0</register_link> as seen from EL1.</para>
    </field_description>
    <field_description order="after">
      <para>When the Effective value of <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.{E2H, TGE} is {1, 1}, this control does not enable the event stream.</para>
    </field_description>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description>
          <para>Disables the event stream.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description>
          <para>Enables the event stream.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
  </field>
  <field id="fieldset_0-1_1" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>EL0VCTEN</field_name>
    <field_msb>1</field_msb>
    <field_lsb>1</field_lsb>
    <rel_range>1</rel_range>
    <field_description order="before"><para>Traps EL0 accesses to the frequency register and virtual counter registers to EL1, or to EL2 when it is implemented and enabled for the current Security state and <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.TGE is 1, as follows:</para>
<list type="unordered">
<listitem><content>In AArch64 state, accesses to the following registers are trapped and reported using EC syndrome value <hexnumber>0x18</hexnumber>:<list type="unordered">
<listitem><content><register_link state="AArch64" id="AArch64-cntvct_el0.xml">CNTVCT_EL0</register_link>.</content>
</listitem><listitem><content><register_link state="AArch64" id="AArch64-cntvctss_el0.xml">CNTVCTSS_EL0</register_link>.</content>
</listitem><listitem><content>If CNTKCTL_EL1.EL0PCTEN is 0, <register_link state="AArch64" id="AArch64-cntfrq_el0.xml">CNTFRQ_EL0</register_link>.</content>
</listitem></list>
</content>
</listitem><listitem><content>In AArch32 state, MRC and MCR accesses to the following registers are trapped and reported using EC syndrome value <hexnumber>0x03</hexnumber>, MRRC and MCRR accesses are trapped and reported using EC syndrome value <hexnumber>0x04</hexnumber>:<list type="unordered">
<listitem><content><register_link state="AArch32" id="AArch32-cntvct.xml">CNTVCT</register_link> and if CNTKCTL_EL1.EL0PCTEN is 0, <register_link state="AArch32" id="AArch32-cntfrq.xml">CNTFRQ</register_link>.</content>
</listitem></list>
</content>
</listitem></list></field_description>
    <field_description order="after">
      <para>When the Effective value of <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.{E2H, TGE} is {1, 1}, this control does not cause any instructions to be trapped.</para>
    </field_description>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description>
          <para>EL0 accesses to the frequency register and virtual counter registers are trapped.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description>
          <para>This control does not cause any instructions to be trapped.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
  </field>
  <field id="fieldset_0-0_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>EL0PCTEN</field_name>
    <field_msb>0</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>0</rel_range>
    <field_description order="before"><para>Traps EL0 accesses to the frequency register and physical counter register to EL1, or to EL2 when it is implemented and enabled for the current Security state and <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.TGE is 1, as follows:</para>
<list type="unordered">
<listitem><content>In AArch64 state, the following registers are trapped and reported using EC syndrome value <hexnumber>0x18</hexnumber>:<list type="unordered">
<listitem><content><register_link state="AArch64" id="AArch64-cntpct_el0.xml">CNTPCT_EL0</register_link></content>
</listitem><listitem><content><register_link state="AArch64" id="AArch64-cntpctss_el0.xml">CNTPCTSS_EL0</register_link></content>
</listitem><listitem><content>If CNTKCTL_EL1.EL0VCTEN is 0, <register_link state="AArch64" id="AArch64-cntfrq_el0.xml">CNTFRQ_EL0</register_link>.</content>
</listitem></list>
</content>
</listitem><listitem><content>In AArch32 state, MCR or MRC accesses the following registers are trapped and reported using EC syndrome value <hexnumber>0x03</hexnumber>, MCRR or MRRC accesses are trapped and reported using EC syndrome value <hexnumber>0x04</hexnumber>:<list type="unordered">
<listitem><content><register_link state="AArch32" id="AArch32-cntpct.xml">CNTPCT</register_link> and if CNTKCTL_EL1.EL0VCTEN is 0, <register_link state="AArch32" id="AArch32-cntfrq.xml">CNTFRQ</register_link>.</content>
</listitem></list>
</content>
</listitem></list></field_description>
    <field_description order="after">
      <para>When the Effective value of <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.{E2H, TGE} is {1, 1}, this control does not cause any instructions to be trapped.</para>
    </field_description>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description>
          <para>EL0 accesses to the frequency register and physical counter register are trapped.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description>
          <para>This control does not cause any instructions to be trapped.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="64">
  <fieldat id="fieldset_0-63_20" msb="63" lsb="20"/>
  <fieldat id="fieldset_0-19_19-1" msb="19" lsb="19"/>
  <fieldat id="fieldset_0-18_18-1" msb="18" lsb="18"/>
  <fieldat id="fieldset_0-17_17-1" msb="17" lsb="17"/>
  <fieldat id="fieldset_0-16_16-1" msb="16" lsb="16"/>
  <fieldat id="fieldset_0-15_15-1" msb="15" lsb="15"/>
  <fieldat id="fieldset_0-14_14-1" msb="14" lsb="14"/>
  <fieldat id="fieldset_0-13_13-1" msb="13" lsb="13"/>
  <fieldat id="fieldset_0-12_12-1" msb="12" lsb="12"/>
  <fieldat id="fieldset_0-11_11-1" msb="11" lsb="11"/>
  <fieldat id="fieldset_0-10_10-1" msb="10" lsb="10"/>
  <fieldat id="fieldset_0-9_9" msb="9" lsb="9"/>
  <fieldat id="fieldset_0-8_8" msb="8" lsb="8"/>
  <fieldat id="fieldset_0-7_4" msb="7" lsb="4"/>
  <fieldat id="fieldset_0-3_3" msb="3" lsb="3"/>
  <fieldat id="fieldset_0-2_2" msb="2" lsb="2"/>
  <fieldat id="fieldset_0-1_1" msb="1" lsb="1"/>
  <fieldat id="fieldset_0-0_0" msb="0" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          


  
    
      <access_permission_text>
        <para>When the Effective value of <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name <value>CNTKCTL_EL1</value> or <value>CNTKCTL_EL12</value> are not guaranteed to be ordered with respect to accesses using the other accessor name.</para>
      </access_permission_text>





    
        
        <access_mechanism accessor="MRS CNTKCTL_EL1" type="SystemAccessor">
            <encoding>
            <access_instruction>MRS &lt;Xt&gt;, CNTKCTL_EL1</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b000"/>
                
                <enc n="CRn" v="0b1110"/>
                
                <enc n="CRm" v="0b0001"/>
                
                <enc n="op2" v="0b000"/>
            </encoding>
            <access_permission>
                <ps name="MRS" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_AA64) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    X{64}(t) = CNTKCTL_EL1();
elsif PSTATE.EL == EL2 then
    if ELIsInHost(EL2) then
        X{64}(t) = CNTHCTL_EL2_VHE(CNTHCTL_EL2());
    else
        X{64}(t) = CNTKCTL_EL1();
    end;
elsif PSTATE.EL == EL3 then
    X{64}(t) = CNTKCTL_EL1();
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>
    
        
        <access_mechanism accessor="MSRregister CNTKCTL_EL1" type="SystemAccessor">
            <encoding>
            <access_instruction>MSR CNTKCTL_EL1, &lt;Xt&gt;</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b000"/>
                
                <enc n="CRn" v="0b1110"/>
                
                <enc n="CRm" v="0b0001"/>
                
                <enc n="op2" v="0b000"/>
            </encoding>
            <access_permission>
                <ps name="MSRregister" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_AA64) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    CNTKCTL_EL1() = X{64}(t);
elsif PSTATE.EL == EL2 then
    if ELIsInHost(EL2) then
        CNTHCTL_EL2() = CNTHCTL_EL2_VHE(X{64}(t));
    else
        CNTKCTL_EL1() = X{64}(t);
    end;
elsif PSTATE.EL == EL3 then
    CNTKCTL_EL1() = X{64}(t);
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>
    
        
        <access_mechanism accessor="MRS CNTKCTL_EL12" type="SystemAccessor">
            <encoding>
            <access_instruction>MRS &lt;Xt&gt;, CNTKCTL_EL12</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b101"/>
                
                <enc n="CRn" v="0b1110"/>
                
                <enc n="CRm" v="0b0001"/>
                
                <enc n="op2" v="0b000"/>
            </encoding>
            <access_condition>
When FEAT_VHE is implemented
            </access_condition>
            <access_permission>
                <ps name="MRS" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_AA64) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if EffectiveHCR_EL2_NVx() IN {'xx1'} then
        AArch64_SystemAccessTrap(EL2, 0x18);
    else
        Undefined();
    end;
elsif PSTATE.EL == EL2 then
    if ELIsInHost(EL2) then
        X{64}(t) = CNTKCTL_EL1();
    else
        Undefined();
    end;
elsif PSTATE.EL == EL3 then
    if ELIsInHost(EL2) then
        X{64}(t) = CNTKCTL_EL1();
    else
        Undefined();
    end;
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>
    
        
        <access_mechanism accessor="MSRregister CNTKCTL_EL12" type="SystemAccessor">
            <encoding>
            <access_instruction>MSR CNTKCTL_EL12, &lt;Xt&gt;</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b101"/>
                
                <enc n="CRn" v="0b1110"/>
                
                <enc n="CRm" v="0b0001"/>
                
                <enc n="op2" v="0b000"/>
            </encoding>
            <access_condition>
When FEAT_VHE is implemented
            </access_condition>
            <access_permission>
                <ps name="MSRregister" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_AA64) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if EffectiveHCR_EL2_NVx() IN {'xx1'} then
        AArch64_SystemAccessTrap(EL2, 0x18);
    else
        Undefined();
    end;
elsif PSTATE.EL == EL2 then
    if ELIsInHost(EL2) then
        CNTKCTL_EL1() = X{64}(t);
    else
        Undefined();
    end;
elsif PSTATE.EL == EL3 then
    if ELIsInHost(EL2) then
        CNTKCTL_EL1() = X{64}(t);
    else
        Undefined();
    end;
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>