CNTP_CVAL_EL0 Counter-timer Physical Timer CompareValue Register when FEAT_AA64 is implemented CNTP_CVAL Architectural AArch32 63 0 63 0 63 0 63 0 Holds the compare value for the EL1 physical timer. Timer CNTP_CVAL_EL0 is a 64-bit register. CompareValue 63 0 63:0 Holds the EL1 physical timer CompareValue. When CNTP_CTL_EL0.ENABLE is 1, and TimerConditionMet is TRUE for the EL1 physical timer, the timer condition is met and all of the following are true: CNTP_CTL_EL0.ISTATUS is set to 1. If CNTP_CTL_EL0.IMASK is 0, an interrupt is generated. TimerConditionMet is defined by 'Operation of the CompareValue views of the timers'. The CompareValue view of the timer acts like a 64-bit upcounter timer. When CNTP_CTL_EL0.ENABLE is 0, the timer condition is not met, but CNTPCT_EL0 continues to count. If the Generic counter is implemented at a size less than 64 bits, then this field is permitted to be implemented at the same width as the counter, and the upper bits are RES0. The value of this field is treated as zero-extended in all counter calculations. AU When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name CNTP_CVAL_EL0 or CNTP_CVAL_EL02 are not guaranteed to be ordered with respect to accesses using the other accessor name. MRS <Xt>, CNTP_CVAL_EL0 if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then if !ELIsInHost(EL0) && CNTKCTL_EL1().EL0PTEN == '0' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && !ELIsInHost(EL2) && CNTHCTL_EL2().EL1PCEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL2) && HCR_EL2().TGE == '0' && CNTHCTL_EL2().EL1PTEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && CNTHCTL_EL2().EL0PTEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then X{64}(t) = CNTHPS_CVAL_EL2(); elsif ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure) then X{64}(t) = CNTHP_CVAL_EL2(); else X{64}(t) = CNTP_CVAL_EL0(); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELIsInHost(EL2) && CNTHCTL_EL2().EL1PCEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL2) && CNTHCTL_EL2().EL1PTEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x178); else X{64}(t) = CNTP_CVAL_EL0(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then X{64}(t) = CNTHPS_CVAL_EL2(); elsif ELIsInHost(EL2) && !IsCurrentSecurityState(SS_Secure) then X{64}(t) = CNTHP_CVAL_EL2(); else X{64}(t) = CNTP_CVAL_EL0(); end; elsif PSTATE.EL == EL3 then X{64}(t) = CNTP_CVAL_EL0(); end; MSR CNTP_CVAL_EL0, <Xt> if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then if !ELIsInHost(EL0) && CNTKCTL_EL1().EL0PTEN == '0' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && !ELIsInHost(EL2) && CNTHCTL_EL2().EL1PCEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL2) && HCR_EL2().TGE == '0' && CNTHCTL_EL2().EL1PTEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && CNTHCTL_EL2().EL0PTEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then CNTHPS_CVAL_EL2() = X{64}(t); elsif ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure) then CNTHP_CVAL_EL2() = X{64}(t); else CNTP_CVAL_EL0() = X{64}(t); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELIsInHost(EL2) && CNTHCTL_EL2().EL1PCEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL2) && CNTHCTL_EL2().EL1PTEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x178) = X{64}(t); else CNTP_CVAL_EL0() = X{64}(t); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then CNTHPS_CVAL_EL2() = X{64}(t); elsif ELIsInHost(EL2) && !IsCurrentSecurityState(SS_Secure) then CNTHP_CVAL_EL2() = X{64}(t); else CNTP_CVAL_EL0() = X{64}(t); end; elsif PSTATE.EL == EL3 then CNTP_CVAL_EL0() = X{64}(t); end; MRS <Xt>, CNTP_CVAL_EL02 When FEAT_VHE is implemented if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then if EL2Enabled() && !ELIsInHost(EL0) && CNTHCTL_EL2().EL1NVPCT == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else X{64}(t) = NVMem(0x178); end; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then X{64}(t) = CNTP_CVAL_EL0(); else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X{64}(t) = CNTP_CVAL_EL0(); else Undefined(); end; end; MSR CNTP_CVAL_EL02, <Xt> When FEAT_VHE is implemented if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then if EL2Enabled() && !ELIsInHost(EL0) && CNTHCTL_EL2().EL1NVPCT == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else NVMem(0x178) = X{64}(t); end; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then CNTP_CVAL_EL0() = X{64}(t); else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then CNTP_CVAL_EL0() = X{64}(t); else Undefined(); end; end; 2026-03-26 20:27:25 2026-03_rel