<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<register_page>
  <registers>
  
    <register execution_state="AArch64" is_register="True" is_internal="True" is_stub_entry="False">
      <reg_short_name>CNTP_TVAL_EL0</reg_short_name>
        
        <reg_long_name>Counter-timer Physical Timer TimerValue Register</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when FEAT_AA64 is implemented</reg_condition>
      




          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        



    
      
      <reg_mapping>
        
  

    

  

    <mapped_name filename="AArch32-cntp_tval.xml">CNTP_TVAL</mapped_name>
  <mapped_type>Architectural</mapped_type>
      <mapped_execution_state>AArch32</mapped_execution_state>
    <mapped_from_startbit>31</mapped_from_startbit>
    <mapped_from_endbit>0</mapped_from_endbit>
    <mapped_to_startbit>31</mapped_to_startbit>
    <mapped_to_endbit>0</mapped_to_endbit>
    <mapped_from_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_from_rangeset>
    <mapped_to_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_to_rangeset>

      </reg_mapping>

      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Holds the timer value for the EL1 physical timer.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>Timer</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>CNTP_TVAL_EL0 is a 64-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="64">
  <text_before_fields/>
  <field id="fieldset_0-63_32" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>63</field_msb>
    <field_lsb>32</field_lsb>
    <rel_range>63:32</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-31_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>TimerValue</field_name>
    <field_msb>31</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>31:0</rel_range>
    <field_description order="before"><para>The TimerValue view of the EL1 physical timer.</para>
<para>On a read of this register:</para>
<list type="unordered">
<listitem><content>If <register_link state="AArch64" id="AArch64-cntp_ctl_el0.xml">CNTP_CTL_EL0</register_link>.ENABLE is 0, the value returned is <arm-defined-word>UNKNOWN</arm-defined-word>.</content>
</listitem><listitem><content>If <register_link state="AArch64" id="AArch64-cntp_ctl_el0.xml">CNTP_CTL_EL0</register_link>.ENABLE is 1, the value returned is (<register_link state="AArch64" id="AArch64-cntp_cval_el0.xml">CNTP_CVAL_EL0</register_link> - <register_link state="AArch64" id="AArch64-cntpct_el0.xml">CNTPCT_EL0</register_link>).</content>
</listitem></list>
<para>On a write of this register, <register_link state="AArch64" id="AArch64-cntp_cval_el0.xml">CNTP_CVAL_EL0</register_link> is set to (<register_link state="AArch64" id="AArch64-cntpct_el0.xml">CNTPCT_EL0</register_link> + TimerValue), where TimerValue is treated as a signed 32-bit integer.</para>
<para>When <register_link state="AArch64" id="AArch64-cntp_ctl_el0.xml">CNTP_CTL_EL0</register_link>.ENABLE is 1, the timer condition is met when (<register_link state="AArch64" id="AArch64-cntpct_el0.xml">CNTPCT_EL0</register_link> - <register_link state="AArch64" id="AArch64-cntp_cval_el0.xml">CNTP_CVAL_EL0</register_link>) is greater than or equal to zero. This means that TimerValue acts like a 32-bit downcounter timer. When the timer condition is met:</para>
<list type="unordered">
<listitem><content><register_link state="AArch64" id="AArch64-cntp_ctl_el0.xml">CNTP_CTL_EL0</register_link>.ISTATUS is set to 1.</content>
</listitem><listitem><content>If <register_link state="AArch64" id="AArch64-cntp_ctl_el0.xml">CNTP_CTL_EL0</register_link>.IMASK is 0, an interrupt is generated.</content>
</listitem></list>
<para>When <register_link state="AArch64" id="AArch64-cntp_ctl_el0.xml">CNTP_CTL_EL0</register_link>.ENABLE is 0, the TimerValue cannot be read but continues to decrement. When the timer is enabled, the TimerValue represents the elapsed time whether that time was spent enabled or disabled.</para>
<note><para>The value of <register_link state="AArch64" id="AArch64-cntpct_el0.xml">CNTPCT_EL0</register_link> used in these calculations is the value seen at the Exception level that the <register_link state="AArch64" id="AArch64-cntpct_el0.xml">CNTPCT_EL0</register_link> register is being read or written from.</para></note></field_description>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="64">
  <fieldat id="fieldset_0-63_32" msb="63" lsb="32"/>
  <fieldat id="fieldset_0-31_0" msb="31" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          


  
    
      <access_permission_text>
        <para>When the Effective value of <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name <value>CNTP_TVAL_EL0</value> or <value>CNTP_TVAL_EL02</value> are not guaranteed to be ordered with respect to accesses using the other accessor name.</para>
      </access_permission_text>





    
        
        <access_mechanism accessor="MRS CNTP_TVAL_EL0" type="SystemAccessor">
            <encoding>
            <access_instruction>MRS &lt;Xt&gt;, CNTP_TVAL_EL0</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b011"/>
                
                <enc n="CRn" v="0b1110"/>
                
                <enc n="CRm" v="0b0010"/>
                
                <enc n="op2" v="0b000"/>
            </encoding>
            <access_permission>
                <ps name="MRS" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_AA64) then
    Undefined();
elsif PSTATE.EL == EL0 then
    if !ELIsInHost(EL0) &amp;&amp; CNTKCTL_EL1().EL0PTEN == '0' then
        if EL2Enabled() &amp;&amp; HCR_EL2().TGE == '1' then
            AArch64_SystemAccessTrap(EL2, 0x18);
        else
            AArch64_SystemAccessTrap(EL1, 0x18);
        end;
    elsif EL2Enabled() &amp;&amp; !ELIsInHost(EL2) &amp;&amp; CNTHCTL_EL2().EL1PCEN == '0' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif ELIsInHost(EL2) &amp;&amp; HCR_EL2().TGE == '0' &amp;&amp; CNTHCTL_EL2().EL1PTEN == '0' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif ELIsInHost(EL0) &amp;&amp; CNTHCTL_EL2().EL0PTEN == '0' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif ELIsInHost(EL0) &amp;&amp; IsCurrentSecurityState(SS_Secure) &amp;&amp; IsFeatureImplemented(FEAT_SEL2) then
        if CNTHPS_CTL_EL2().ENABLE == '0' then
            X{64}(t) = ARBITRARY:bits(64);
        else
            X{64}(t) = ZeroExtend{64}((CNTHPS_CVAL_EL2() - PhysicalCountInt())[31:0]);
        end;
    elsif ELIsInHost(EL0) &amp;&amp; !IsCurrentSecurityState(SS_Secure) then
        if CNTHP_CTL_EL2().ENABLE == '0' then
            X{64}(t) = ARBITRARY:bits(64);
        else
            X{64}(t) = ZeroExtend{64}((CNTHP_CVAL_EL2() - PhysicalCountInt())[31:0]);
        end;
    elsif IsFeatureImplemented(FEAT_ECV_POFF) &amp;&amp; EL2Enabled() &amp;&amp; (!HaveEL(EL3) || SCR_EL3().ECVEn == '1') &amp;&amp; CNTHCTL_EL2().ECV == '1' &amp;&amp; !ELIsInHost(EL0) then
        if CNTP_CTL_EL0().ENABLE == '0' then
            X{64}(t) = ARBITRARY:bits(64);
        else
            X{64}(t) = ZeroExtend{64}((CNTP_CVAL_EL0() - (PhysicalCountInt() - CNTPOFF_EL2()))[31:0]);
        end;
    else
        if CNTP_CTL_EL0().ENABLE == '0' then
            X{64}(t) = ARBITRARY:bits(64);
        else
            X{64}(t) = ZeroExtend{64}((CNTP_CVAL_EL0() - PhysicalCountInt())[31:0]);
        end;
    end;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELIsInHost(EL2) &amp;&amp; CNTHCTL_EL2().EL1PCEN == '0' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif ELIsInHost(EL2) &amp;&amp; CNTHCTL_EL2().EL1PTEN == '0' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif IsFeatureImplemented(FEAT_ECV_POFF) &amp;&amp; EL2Enabled() &amp;&amp; (!HaveEL(EL3) || SCR_EL3().ECVEn == '1') &amp;&amp; CNTHCTL_EL2().ECV == '1' then
        if CNTP_CTL_EL0().ENABLE == '0' then
            X{64}(t) = ARBITRARY:bits(64);
        else
            X{64}(t) = ZeroExtend{64}((CNTP_CVAL_EL0() - (PhysicalCountInt() - CNTPOFF_EL2()))[31:0]);
        end;
    else
        if CNTP_CTL_EL0().ENABLE == '0' then
            X{64}(t) = ARBITRARY:bits(64);
        else
            X{64}(t) = ZeroExtend{64}((CNTP_CVAL_EL0() - PhysicalCountInt())[31:0]);
        end;
    end;
elsif PSTATE.EL == EL2 then
    if ELIsInHost(EL2) &amp;&amp; IsCurrentSecurityState(SS_Secure) &amp;&amp; IsFeatureImplemented(FEAT_SEL2) then
        if CNTHPS_CTL_EL2().ENABLE == '0' then
            X{64}(t) = ARBITRARY:bits(64);
        else
            X{64}(t) = ZeroExtend{64}((CNTHPS_CVAL_EL2() - PhysicalCountInt())[31:0]);
        end;
    elsif ELIsInHost(EL2) &amp;&amp; !IsCurrentSecurityState(SS_Secure) then
        if CNTHP_CTL_EL2().ENABLE == '0' then
            X{64}(t) = ARBITRARY:bits(64);
        else
            X{64}(t) = ZeroExtend{64}((CNTHP_CVAL_EL2() - PhysicalCountInt())[31:0]);
        end;
    else
        if CNTP_CTL_EL0().ENABLE == '0' then
            X{64}(t) = ARBITRARY:bits(64);
        else
            X{64}(t) = ZeroExtend{64}((CNTP_CVAL_EL0() - PhysicalCountInt())[31:0]);
        end;
    end;
elsif PSTATE.EL == EL3 then
    if CNTP_CTL_EL0().ENABLE == '0' then
        X{64}(t) = ARBITRARY:bits(64);
    else
        X{64}(t) = ZeroExtend{64}((CNTP_CVAL_EL0() - PhysicalCountInt())[31:0]);
    end;
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>
    
        
        <access_mechanism accessor="MSRregister CNTP_TVAL_EL0" type="SystemAccessor">
            <encoding>
            <access_instruction>MSR CNTP_TVAL_EL0, &lt;Xt&gt;</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b011"/>
                
                <enc n="CRn" v="0b1110"/>
                
                <enc n="CRm" v="0b0010"/>
                
                <enc n="op2" v="0b000"/>
            </encoding>
            <access_permission>
                <ps name="MSRregister" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_AA64) then
    Undefined();
elsif PSTATE.EL == EL0 then
    if !ELIsInHost(EL0) &amp;&amp; CNTKCTL_EL1().EL0PTEN == '0' then
        if EL2Enabled() &amp;&amp; HCR_EL2().TGE == '1' then
            AArch64_SystemAccessTrap(EL2, 0x18);
        else
            AArch64_SystemAccessTrap(EL1, 0x18);
        end;
    elsif EL2Enabled() &amp;&amp; !ELIsInHost(EL2) &amp;&amp; CNTHCTL_EL2().EL1PCEN == '0' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif ELIsInHost(EL2) &amp;&amp; HCR_EL2().TGE == '0' &amp;&amp; CNTHCTL_EL2().EL1PTEN == '0' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif ELIsInHost(EL0) &amp;&amp; CNTHCTL_EL2().EL0PTEN == '0' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif ELIsInHost(EL0) &amp;&amp; IsCurrentSecurityState(SS_Secure) &amp;&amp; IsFeatureImplemented(FEAT_SEL2) then
        CNTHPS_CVAL_EL2() = SignExtend{64}(X{64}(t)[31:0]) + PhysicalCountInt();
    elsif ELIsInHost(EL0) &amp;&amp; !IsCurrentSecurityState(SS_Secure) then
        CNTHP_CVAL_EL2() = SignExtend{64}(X{64}(t)[31:0]) + PhysicalCountInt();
    elsif IsFeatureImplemented(FEAT_ECV_POFF) &amp;&amp; EL2Enabled() &amp;&amp; (!HaveEL(EL3) || SCR_EL3().ECVEn == '1') &amp;&amp; CNTHCTL_EL2().ECV == '1' &amp;&amp; !ELIsInHost(EL0) then
        CNTP_CVAL_EL0() = (SignExtend{64}(X{64}(t)[31:0]) + PhysicalCountInt()) - CNTPOFF_EL2();
    else
        CNTP_CVAL_EL0() = SignExtend{64}(X{64}(t)[31:0]) + PhysicalCountInt();
    end;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELIsInHost(EL2) &amp;&amp; CNTHCTL_EL2().EL1PCEN == '0' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif ELIsInHost(EL2) &amp;&amp; CNTHCTL_EL2().EL1PTEN == '0' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif IsFeatureImplemented(FEAT_ECV_POFF) &amp;&amp; EL2Enabled() &amp;&amp; (!HaveEL(EL3) || SCR_EL3().ECVEn == '1') &amp;&amp; CNTHCTL_EL2().ECV == '1' then
        CNTP_CVAL_EL0() = (SignExtend{64}(X{64}(t)[31:0]) + PhysicalCountInt()) - CNTPOFF_EL2();
    else
        CNTP_CVAL_EL0() = SignExtend{64}(X{64}(t)[31:0]) + PhysicalCountInt();
    end;
elsif PSTATE.EL == EL2 then
    if ELIsInHost(EL2) &amp;&amp; IsCurrentSecurityState(SS_Secure) &amp;&amp; IsFeatureImplemented(FEAT_SEL2) then
        CNTHPS_CVAL_EL2() = SignExtend{64}(X{64}(t)[31:0]) + PhysicalCountInt();
    elsif ELIsInHost(EL2) &amp;&amp; !IsCurrentSecurityState(SS_Secure) then
        CNTHP_CVAL_EL2() = SignExtend{64}(X{64}(t)[31:0]) + PhysicalCountInt();
    else
        CNTP_CVAL_EL0() = SignExtend{64}(X{64}(t)[31:0]) + PhysicalCountInt();
    end;
elsif PSTATE.EL == EL3 then
    CNTP_CVAL_EL0() = SignExtend{64}(X{64}(t)[31:0]) + PhysicalCountInt();
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>
    
        
        <access_mechanism accessor="MRS CNTP_TVAL_EL02" type="SystemAccessor">
            <encoding>
            <access_instruction>MRS &lt;Xt&gt;, CNTP_TVAL_EL02</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b101"/>
                
                <enc n="CRn" v="0b1110"/>
                
                <enc n="CRm" v="0b0010"/>
                
                <enc n="op2" v="0b000"/>
            </encoding>
            <access_condition>
When FEAT_VHE is implemented
            </access_condition>
            <access_permission>
                <ps name="MRS" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_AA64) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if EffectiveHCR_EL2_NVx() IN {'xx1'} then
        AArch64_SystemAccessTrap(EL2, 0x18);
    else
        Undefined();
    end;
elsif PSTATE.EL == EL2 then
    if ELIsInHost(EL2) then
        if CNTP_CTL_EL0().ENABLE == '0' then
            X{64}(t) = ARBITRARY:bits(64);
        else
            X{64}(t) = ZeroExtend{64}((CNTP_CVAL_EL0() - PhysicalCountInt())[31:0]);
        end;
    else
        Undefined();
    end;
elsif PSTATE.EL == EL3 then
    if ELIsInHost(EL2) then
        if CNTP_CTL_EL0().ENABLE == '0' then
            X{64}(t) = ARBITRARY:bits(64);
        else
            X{64}(t) = ZeroExtend{64}((CNTP_CVAL_EL0() - PhysicalCountInt())[31:0]);
        end;
    else
        Undefined();
    end;
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>
    
        
        <access_mechanism accessor="MSRregister CNTP_TVAL_EL02" type="SystemAccessor">
            <encoding>
            <access_instruction>MSR CNTP_TVAL_EL02, &lt;Xt&gt;</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b101"/>
                
                <enc n="CRn" v="0b1110"/>
                
                <enc n="CRm" v="0b0010"/>
                
                <enc n="op2" v="0b000"/>
            </encoding>
            <access_condition>
When FEAT_VHE is implemented
            </access_condition>
            <access_permission>
                <ps name="MSRregister" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_AA64) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if EffectiveHCR_EL2_NVx() IN {'xx1'} then
        AArch64_SystemAccessTrap(EL2, 0x18);
    else
        Undefined();
    end;
elsif PSTATE.EL == EL2 then
    if ELIsInHost(EL2) then
        CNTP_CVAL_EL0() = SignExtend{64}(X{64}(t)[31:0]) + PhysicalCountInt();
    else
        Undefined();
    end;
elsif PSTATE.EL == EL3 then
    if ELIsInHost(EL2) then
        CNTP_CVAL_EL0() = SignExtend{64}(X{64}(t)[31:0]) + PhysicalCountInt();
    else
        Undefined();
    end;
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>