<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
<!-- Copyright (c) 2010-2026 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
<!--The data contained in this document is preliminary and subject to change or correction following further review. -->
<?xml-stylesheet href="one_register.xsl" type="text/xsl" ?>







<register_page>
  <registers>
  
    <register execution_state="AArch64" is_register="True" is_internal="True" is_stub_entry="False">
      <reg_short_name>CNTPOFF_EL2</reg_short_name>
        
        <reg_long_name>Counter-timer Physical Offset Register</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when FEAT_ECV_POFF is implemented and FEAT_AA64 is implemented</reg_condition>
      




          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Holds the 64-bit physical offset. This is the offset for the AArch64 EL1 physical timer and counter when Enhanced Counter Virtualization is enabled.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>Timer</reg_group>
      </reg_groups>
      <reg_configuration>
        
    
      <configuration_text>
        <para>The physical offset applies to:</para>

      </configuration_text>
      <configuration_text>
        <list type="unordered">
<listitem><content>Direct reads of <register_link state="AArch64" id="AArch64-cntpct_el0.xml">CNTPCT_EL0</register_link> from EL0 or EL1.</content>
</listitem><listitem><content>Indirect reads of the physical counter by the EL1 physical timer. See <xref linkend="#CCHGGDGB">'The Generic Timer in AArch64 state'</xref>.</content>
</listitem><listitem><content>Indirect reads of the physical counter for timestamps generated by profiling logic. See 'The Statistical Profiling Extension' and <xref linkend="#BABBDIGF">'AArch64 Self-hosted Trace'</xref>.</content>
</listitem></list>

      </configuration_text>
      <configuration_text>
        <para>The physical offset only applies under conditions described by the relevant sections.</para>

      </configuration_text>
      <configuration_text>
        <para>If EL2 is not implemented, this register is <arm-defined-word>RES0</arm-defined-word> from EL3.</para>
      </configuration_text>

      </reg_configuration>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>CNTPOFF_EL2 is a 64-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="64">
  <text_before_fields/>
  <field id="fieldset_0-63_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>PO</field_name>
    <field_shortdesc>Physical offset</field_shortdesc>
    <field_msb>63</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>63:0</rel_range>
    <field_description order="before">
      <para>Physical offset.</para>
    </field_description>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="64">
  <fieldat id="fieldset_0-63_0" msb="63" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          






    
        
        <access_mechanism accessor="MRS CNTPOFF_EL2" type="SystemAccessor">
            <encoding>
            <access_instruction>MRS &lt;Xt&gt;, CNTPOFF_EL2</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b100"/>
                
                <enc n="CRn" v="0b1110"/>
                
                <enc n="CRm" v="0b0000"/>
                
                <enc n="op2" v="0b110"/>
            </encoding>
            <access_permission>
                <ps name="MRS" sections="1" secttype="access_permission">
                <pstext>
if !(IsFeatureImplemented(FEAT_ECV_POFF) &amp;&amp; IsFeatureImplemented(FEAT_AA64)) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if EffectiveHCR_EL2_NVx() IN {'1x1'} then
        X{64}(t) = NVMem(0x1A8);
    elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then
        AArch64_SystemAccessTrap(EL2, 0x18);
    else
        Undefined();
    end;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; SCR_EL3().ECVEn == '0' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; SCR_EL3().ECVEn == '0' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        X{64}(t) = CNTPOFF_EL2();
    end;
elsif PSTATE.EL == EL3 then
    X{64}(t) = CNTPOFF_EL2();
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>
    
        
        <access_mechanism accessor="MSRregister CNTPOFF_EL2" type="SystemAccessor">
            <encoding>
            <access_instruction>MSR CNTPOFF_EL2, &lt;Xt&gt;</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b100"/>
                
                <enc n="CRn" v="0b1110"/>
                
                <enc n="CRm" v="0b0000"/>
                
                <enc n="op2" v="0b110"/>
            </encoding>
            <access_permission>
                <ps name="MSRregister" sections="1" secttype="access_permission">
                <pstext>
if !(IsFeatureImplemented(FEAT_ECV_POFF) &amp;&amp; IsFeatureImplemented(FEAT_AA64)) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if EffectiveHCR_EL2_NVx() IN {'1x1'} then
        NVMem(0x1A8) = X{64}(t);
    elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then
        AArch64_SystemAccessTrap(EL2, 0x18);
    else
        Undefined();
    end;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; SCR_EL3().ECVEn == '0' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; SCR_EL3().ECVEn == '0' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        CNTPOFF_EL2() = X{64}(t);
    end;
elsif PSTATE.EL == EL3 then
    CNTPOFF_EL2() = X{64}(t);
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>