<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
<!-- Copyright (c) 2010-2026 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
<!--The data contained in this document is preliminary and subject to change or correction following further review. -->
<?xml-stylesheet href="one_register.xsl" type="text/xsl" ?>







<register_page>
  <registers>
  
    <register execution_state="AArch64" is_register="True" is_internal="True" is_stub_entry="False">
      <reg_short_name>CNTPS_CVAL_EL1</reg_short_name>
        
        <reg_long_name>Counter-timer Physical Secure Timer CompareValue Register</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when EL3 is implemented and FEAT_AA64 is implemented</reg_condition>
      




          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Holds the compare value for the secure physical timer, usually accessible at EL3 but configurably accessible at EL1 in Secure state.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>Timer</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>CNTPS_CVAL_EL1 is a 64-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="64">
  <text_before_fields/>
  <field id="fieldset_0-63_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>CompareValue</field_name>
    <field_msb>63</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>63:0</rel_range>
    <field_description order="before"><para>Holds the secure physical timer CompareValue.</para>
<para>When <register_link state="AArch64" id="AArch64-cntps_ctl_el1.xml">CNTPS_CTL_EL1</register_link>.ENABLE is 1, and TimerConditionMet is TRUE for the EL1 secure physical timer, the timer condition is met and all of the following are true:</para>
<list type="unordered">
<listitem><content><register_link state="AArch64" id="AArch64-cntps_ctl_el1.xml">CNTPS_CTL_EL1</register_link>.ISTATUS is set to 1.</content>
</listitem><listitem><content>If <register_link state="AArch64" id="AArch64-cntps_ctl_el1.xml">CNTPS_CTL_EL1</register_link>.IMASK is 0, an interrupt is generated.</content>
</listitem></list>
<para>TimerConditionMet is defined by <xref linkend="#CHDDAEAJ">'Operation of the CompareValue views of the timers'</xref>.</para>
<para>The CompareValue view of the timer acts like a 64-bit upcounter timer.</para>
<para>When <register_link state="AArch64" id="AArch64-cntps_ctl_el1.xml">CNTPS_CTL_EL1</register_link>.ENABLE is 0, the timer condition is not met, but <register_link state="AArch64" id="AArch64-cntpct_el0.xml">CNTPCT_EL0</register_link> continues to count.</para>
<para>If the Generic counter is implemented at a size less than 64 bits, then this field is permitted to be implemented at the same width as the counter, and the upper bits are <arm-defined-word>RES0</arm-defined-word>.</para>
<para>The value of this field is treated as zero-extended in all counter calculations.</para></field_description>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="64">
  <fieldat id="fieldset_0-63_0" msb="63" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          






    
        
        <access_mechanism accessor="MRS CNTPS_CVAL_EL1" type="SystemAccessor">
            <encoding>
            <access_instruction>MRS &lt;Xt&gt;, CNTPS_CVAL_EL1</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b111"/>
                
                <enc n="CRn" v="0b1110"/>
                
                <enc n="CRm" v="0b0010"/>
                
                <enc n="op2" v="0b010"/>
            </encoding>
            <access_permission>
                <ps name="MRS" sections="1" secttype="access_permission">
                <pstext>
if !(HaveEL(EL3) &amp;&amp; IsFeatureImplemented(FEAT_AA64)) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if HaveEL(EL3) &amp;&amp; SCR_EL3().NS == '0' then
        if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; SCR_EL3().ST == '0' then
            Undefined();
        elsif SCR_EL3().EEL2 == '1' then
            Undefined();
        elsif SCR_EL3().ST == '0' then
            if EL3SDDUndef() then
                Undefined();
            else
                AArch64_SystemAccessTrap(EL3, 0x18);
            end;
        else
            X{64}(t) = CNTPS_CVAL_EL1();
        end;
    else
        Undefined();
    end;
elsif PSTATE.EL == EL2 then
    Undefined();
elsif PSTATE.EL == EL3 then
    X{64}(t) = CNTPS_CVAL_EL1();
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>
    
        
        <access_mechanism accessor="MSRregister CNTPS_CVAL_EL1" type="SystemAccessor">
            <encoding>
            <access_instruction>MSR CNTPS_CVAL_EL1, &lt;Xt&gt;</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b111"/>
                
                <enc n="CRn" v="0b1110"/>
                
                <enc n="CRm" v="0b0010"/>
                
                <enc n="op2" v="0b010"/>
            </encoding>
            <access_permission>
                <ps name="MSRregister" sections="1" secttype="access_permission">
                <pstext>
if !(HaveEL(EL3) &amp;&amp; IsFeatureImplemented(FEAT_AA64)) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if HaveEL(EL3) &amp;&amp; SCR_EL3().NS == '0' then
        if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; SCR_EL3().ST == '0' then
            Undefined();
        elsif SCR_EL3().EEL2 == '1' then
            Undefined();
        elsif SCR_EL3().ST == '0' then
            if EL3SDDUndef() then
                Undefined();
            else
                AArch64_SystemAccessTrap(EL3, 0x18);
            end;
        else
            CNTPS_CVAL_EL1() = X{64}(t);
        end;
    else
        Undefined();
    end;
elsif PSTATE.EL == EL2 then
    Undefined();
elsif PSTATE.EL == EL3 then
    CNTPS_CVAL_EL1() = X{64}(t);
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>