CNTVOFF_EL2 Counter-timer Virtual Offset Register when FEAT_AA64 is implemented CNTVOFF Architectural AArch32 63 0 63 0 63 0 63 0 Holds the 64-bit virtual offset. This is the offset for the AArch64 virtual timers and counters. Virt The virtual offset applies to: Direct reads of CNTVCT_EL0. Indirect reads of the virtual counter by the EL1 virtual timer. See 'The Generic Timer in AArch64 state'. Indirect reads of the virtual counter for timestamps generated by profiling logic. See 'The Statistical Profiling Extension' and 'AArch64 Self-hosted Trace'. The virtual offset only applies under conditions described by the relevant sections. CNTVOFF_EL2 is a 64-bit register. VOffset Virtual offset 63 0 63:0 Virtual offset. If the Generic counter is implemented at a size less than 64 bits, then this field is permitted to be implemented at the same width as the counter, and the upper bits are RES0. The value of this field is treated as zero-extended in all counter calculations. AU MRS <Xt>, CNTVOFF_EL2 if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x060); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then X{64}(t) = CNTVOFF_EL2(); elsif PSTATE.EL == EL3 then X{64}(t) = CNTVOFF_EL2(); end; MSR CNTVOFF_EL2, <Xt> if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x060) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then CNTVOFF_EL2() = X{64}(t); elsif PSTATE.EL == EL3 then CNTVOFF_EL2() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel