<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<register_page>
  <registers>
  
    <register execution_state="AArch64" is_register="True" is_internal="True" is_stub_entry="False">
      <reg_short_name>CONTEXTIDR_EL1</reg_short_name>
        
        <reg_long_name>Context ID Register (EL1)</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when FEAT_AA64 is implemented</reg_condition>
      




          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        



    
      
      <reg_mapping>
        
  

    

  

    <mapped_name filename="AArch32-contextidr.xml">CONTEXTIDR</mapped_name>
  <mapped_type>Architectural</mapped_type>
      <mapped_execution_state>AArch32</mapped_execution_state>
    <mapped_from_startbit>31</mapped_from_startbit>
    <mapped_from_endbit>0</mapped_from_endbit>
    <mapped_to_startbit>31</mapped_to_startbit>
    <mapped_to_endbit>0</mapped_to_endbit>
    <mapped_from_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_from_rangeset>
    <mapped_to_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_to_rangeset>

      </reg_mapping>

      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Identifies the current Process Identifier.</para>

      </purpose_text>
      <purpose_text>
        <para>The value of the whole of this register is called the Context ID and is used by:</para>

      </purpose_text>
      <purpose_text>
        <list type="unordered">
<listitem><content>The debug logic, for Linked and Unlinked Context ID matching.</content>
</listitem><listitem><content>The trace logic, to identify the current process.</content>
</listitem></list>

      </purpose_text>
      <purpose_text>
        <para>The significance of this register is for debug and trace use only.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
            <reg_group>Memory</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>CONTEXTIDR_EL1 is a 64-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="64">
  <text_before_fields/>
  <field id="fieldset_0-63_32" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>63</field_msb>
    <field_lsb>32</field_lsb>
    <rel_range>63:32</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-31_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>PROCID</field_name>
    <field_msb>31</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>31:0</rel_range>
    <field_description order="before"><para>Process Identifier. This field must be programmed with a unique value that identifies the current process.</para>
<note><para>In AArch32 state, when <register_link state="AArch32" id="AArch32-ttbcr.xml">TTBCR</register_link>.EAE is set to 0, <register_link state="AArch32" id="AArch32-contextidr.xml">CONTEXTIDR</register_link>.ASID holds the ASID.</para><para>In AArch64 state, CONTEXTIDR_EL1 is independent of the ASID, and for the EL1&amp;0 translation regime either <register_link state="AArch64" id="AArch64-ttbr0_el1.xml">TTBR0_EL1</register_link> or <register_link state="AArch64" id="AArch64-ttbr1_el1.xml">TTBR1_EL1</register_link> holds the ASID.</para></note></field_description>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="64">
  <fieldat id="fieldset_0-63_32" msb="63" lsb="32"/>
  <fieldat id="fieldset_0-31_0" msb="31" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          


  
    
      <access_permission_text>
        <para>When the Effective value of <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name <value>CONTEXTIDR_EL1</value> or <value>CONTEXTIDR_EL12</value> are not guaranteed to be ordered with respect to accesses using the other accessor name.</para>
      </access_permission_text>





    
        
        <access_mechanism accessor="MRS CONTEXTIDR_EL1" type="SystemAccessor">
            <encoding>
            <access_instruction>MRS &lt;Xt&gt;, CONTEXTIDR_EL1</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b000"/>
                
                <enc n="CRn" v="0b1101"/>
                
                <enc n="CRm" v="0b0000"/>
                
                <enc n="op2" v="0b001"/>
            </encoding>
            <access_permission>
                <ps name="MRS" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_AA64) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; HCR_EL2().TRVM == '1' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT) &amp;&amp; (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') &amp;&amp; HFGRTR_EL2().CONTEXTIDR_EL1 == '1' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif EffectiveHCR_EL2_NVx() IN {'111'} then
        X{64}(t) = NVMem(0x108);
    else
        X{64}(t) = CONTEXTIDR_EL1();
    end;
elsif PSTATE.EL == EL2 then
    if ELIsInHost(EL2) then
        X{64}(t) = CONTEXTIDR_EL2();
    else
        X{64}(t) = CONTEXTIDR_EL1();
    end;
elsif PSTATE.EL == EL3 then
    X{64}(t) = CONTEXTIDR_EL1();
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>
    
        
        <access_mechanism accessor="MSRregister CONTEXTIDR_EL1" type="SystemAccessor">
            <encoding>
            <access_instruction>MSR CONTEXTIDR_EL1, &lt;Xt&gt;</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b000"/>
                
                <enc n="CRn" v="0b1101"/>
                
                <enc n="CRm" v="0b0000"/>
                
                <enc n="op2" v="0b001"/>
            </encoding>
            <access_permission>
                <ps name="MSRregister" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_AA64) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; HCR_EL2().TVM == '1' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT) &amp;&amp; (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') &amp;&amp; HFGWTR_EL2().CONTEXTIDR_EL1 == '1' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif EffectiveHCR_EL2_NVx() IN {'111'} then
        NVMem(0x108) = X{64}(t);
    else
        CONTEXTIDR_EL1() = X{64}(t);
    end;
elsif PSTATE.EL == EL2 then
    if ELIsInHost(EL2) then
        CONTEXTIDR_EL2() = X{64}(t);
    else
        CONTEXTIDR_EL1() = X{64}(t);
    end;
elsif PSTATE.EL == EL3 then
    CONTEXTIDR_EL1() = X{64}(t);
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>
    
        
        <access_mechanism accessor="MRS CONTEXTIDR_EL12" type="SystemAccessor">
            <encoding>
            <access_instruction>MRS &lt;Xt&gt;, CONTEXTIDR_EL12</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b101"/>
                
                <enc n="CRn" v="0b1101"/>
                
                <enc n="CRm" v="0b0000"/>
                
                <enc n="op2" v="0b001"/>
            </encoding>
            <access_condition>
When FEAT_VHE is implemented
            </access_condition>
            <access_permission>
                <ps name="MRS" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_AA64) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if EffectiveHCR_EL2_NVx() == '101' then
        X{64}(t) = NVMem(0x108);
    elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then
        AArch64_SystemAccessTrap(EL2, 0x18);
    else
        Undefined();
    end;
elsif PSTATE.EL == EL2 then
    if ELIsInHost(EL2) then
        X{64}(t) = CONTEXTIDR_EL1();
    else
        Undefined();
    end;
elsif PSTATE.EL == EL3 then
    if ELIsInHost(EL2) then
        X{64}(t) = CONTEXTIDR_EL1();
    else
        Undefined();
    end;
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>
    
        
        <access_mechanism accessor="MSRregister CONTEXTIDR_EL12" type="SystemAccessor">
            <encoding>
            <access_instruction>MSR CONTEXTIDR_EL12, &lt;Xt&gt;</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b101"/>
                
                <enc n="CRn" v="0b1101"/>
                
                <enc n="CRm" v="0b0000"/>
                
                <enc n="op2" v="0b001"/>
            </encoding>
            <access_condition>
When FEAT_VHE is implemented
            </access_condition>
            <access_permission>
                <ps name="MSRregister" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_AA64) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if EffectiveHCR_EL2_NVx() == '101' then
        NVMem(0x108) = X{64}(t);
    elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then
        AArch64_SystemAccessTrap(EL2, 0x18);
    else
        Undefined();
    end;
elsif PSTATE.EL == EL2 then
    if ELIsInHost(EL2) then
        CONTEXTIDR_EL1() = X{64}(t);
    else
        Undefined();
    end;
elsif PSTATE.EL == EL3 then
    if ELIsInHost(EL2) then
        CONTEXTIDR_EL1() = X{64}(t);
    else
        Undefined();
    end;
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>