COSP RCTX
Clear Other Speculative Prediction Restriction by Context
when FEAT_SPECRES2 is implemented and FEAT_AA64 is implemented
Clear Other Speculative Prediction Restriction by Context applies to all prediction resources not managed by other speculation restriction System instructions.
The actions of code in the target execution context or contexts appearing in program order before the instruction cannot exploitatively control any predictions occurring after the instruction is complete and synchronized.
This instruction applies to all speculative access except:
Cache Prefetch predictions.
Control Flow predictions.
Data Value predictions.
This instruction is guaranteed to be complete following a DSB that covers both read and write behavior on the PE that executed the original restriction instruction, and a subsequent Context Synchronization event is required to ensure that the effect of the completion of the instructions is synchronized to the current execution.
This instruction does not require the invalidation of Cache Allocation Resources so long as the behavior described for completion of this instruction is met by the implementation.On some implementations, the instruction is likely to take a significant number of cycles to execute. This instruction is expected to be used rarely, such as on the roll-over of an ASID or VMID, but should not be used on every context switch.This instruction applies to speculative accesses resulting from address predictions.
Predictor Maintenance Instructions
COSP RCTX is a 64-bit System instruction.
63
49
63:49
Reserved, RES0.
GVMID
48
48
48
Execution of this instruction applies to all VMIDs or a specified VMID.
For target execution contexts other than EL0 and EL1, this field is RES0.
If the instruction is executed at EL0 or EL1, this field has an Effective value of 0.
If EL2 is not implemented or not enabled for the target Security state, this field is RES0.
0b0
Applies to specified VMID for an EL0 or EL1 target execution context.
0b1
Applies to all VMIDs for an EL0 or EL1 target execution context.
VMID
47
32
47:32
Only applies when bit[48] is 0 and the target execution context is either:
EL1.
EL0 when the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}.
Otherwise this field is RES0.
When the instruction is executed at EL1, this field is treated as the current VMID.
When the instruction is executed at EL0 and the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, this field is treated as the current VMID.
When the instruction is executed at EL0 and the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this field is ignored.
If EL2 is not implemented or not enabled for the target Security state, this field is RES0.
If the implementation supports 16 bits of VMID, then the upper 8 bits of the VMID must be written to 0 by software when the context being affected only uses 8 bits.
31
28
31:28
Reserved, RES0.
NSE
27
27
0
Together with the NS field, selects the Security state.
For a description of the values derived by evaluating NS and NSE together, see COSP_RCTX.NS.
When FEAT_RME is implemented
27
27
27
Reserved, RES0.
Otherwise
NS
26
26
0
Together with the NSE field, selects the Security state.
NSENSMeaning
0b00b0When Secure state is implemented, Secure. Otherwise reserved.
0b00b1Non-secure.
0b10b0Root.
0b10b1Realm.
Some Effective values are determined by the current Security state:
When executed in Secure state, the Effective value of NSE is 0.
When executed in Non-secure state, the Effective value of {NSE, NS} is {0, 1}.
When executed in Realm state, the Effective value of {NSE, NS} is {1, 1}.
This instruction is treated as a NOP when executed at EL3 and either:
COSP_RCTX.{NSE, NS} selects a reserved value.
COSP_RCTX.{NSE, NS} == {1, 0} and COSP_RCTX.EL has a value other than 0b11.
When FEAT_RME is implemented
NS
26
26
0
Security State.
When executed in Non-secure state, the Effective value of NS is 1.
0b0
Secure state.
0b1
Non-secure state.
Otherwise
EL
25
24
25:24
Exception Level. Indicates the Exception level of the target execution context.
If the instruction is executed at an Exception level lower than the specified level, or is specified to apply to a combination of Exception level and Security state that is not implemented, this instruction is treated as a NOP.
0b00
EL0.
0b01
EL1
0b10
EL2
When FEAT_EL2 is implemented
0b11
EL3
When FEAT_EL3 is implemented
23
17
23:17
Reserved, RES0.
GASID
16
16
16
Execution of this instruction applies to all ASIDs, or a specified ASID.
For target execution contexts other than EL0, this field is RES0.
If the instruction is executed at EL0, this field has an Effective value of 0.
0b0
Applies to specified ASID for an EL0 target execution context.
0b1
Applies to all ASIDs for an EL0 target execution context.
ASID
15
0
15:0
Only applies to an EL0 target execution context and when bit[16] is 0.
Otherwise, this field is RES0.
When the instruction is executed at EL0, this field is treated as the current ASID.
If the implementation supports 16 bits of ASID, then the upper 8 bits of the ASID must be written to 0 by software when the context being affected only uses 8 bits.
This system instruction is an alias of the SYS instruction.
COSP RCTX, <Xt>
if !(IsFeatureImplemented(FEAT_SPECRES2) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif PSTATE.EL == EL0 then
if !ELIsInHost(EL0) && SCTLR_EL1().EnRCTX == '0' then
if EL2Enabled() && HCR_EL2().TGE == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
else
AArch64_SystemAccessTrap(EL1, 0x18);
end;
elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().COSPRCTX == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif ELIsInHost(EL0) && SCTLR_EL2().EnRCTX == '0' then
AArch64_SystemAccessTrap(EL2, 0x18);
else
AArch64_RestrictPrediction(X{64}(t), RestrictType_Other);
end;
elsif PSTATE.EL == EL1 then
if EffectiveHCR_EL2_NVx() IN {'xx1'} then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().COSPRCTX == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
else
AArch64_RestrictPrediction(X{64}(t), RestrictType_Other);
end;
elsif PSTATE.EL == EL2 then
AArch64_RestrictPrediction(X{64}(t), RestrictType_Other);
elsif PSTATE.EL == EL3 then
AArch64_RestrictPrediction(X{64}(t), RestrictType_Other);
end;
2026-03-26 20:27:25
2026-03_rel