CPACR_EL1
Architectural Feature Access Control Register
when FEAT_AA64 is implemented
CPACR
Architectural
AArch32
31
0
31
0
31
0
31
0
Controls access to trace,
SME, Streaming SVE,
SVE,
and Advanced SIMD and floating-point functionality.
Other
CPACR_EL1 is a 64-bit register.
63
32
63:32
Reserved, RES0.
TCPAC
31
31
0
Reserved for software use in nested virtualization.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
CPACRMASK_EL1.TCPAC == '1'
RO
When FEAT_NV2p1 is implemented
31
31
31
Reserved, RES0.
Otherwise
TAM
30
30
0
Reserved for software use in nested virtualization.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
CPACRMASK_EL1.TAM == '1'
RO
When FEAT_AMUv1 is implemented and FEAT_NV2p1 is implemented
30
30
30
Reserved, RES0.
Otherwise
E0POE
29
29
0
Enable access to POR_EL0.
Traps EL0 accesses to POR_EL0, from AArch64 state only to EL1, or to EL2 when it is implemented and enabled in the current Security state and HCR_EL2.TGE is 1. The exception is reported using EC syndrome value 0x18.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this field has no effect on execution at EL0.
0b0
This control causes EL0 access to POR_EL0 to be trapped.
0b1
This control does not cause any instructions to be trapped.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
CPACRMASK_EL1.E0POE == '1'
RO
When FEAT_S1POE is implemented
29
29
29
Reserved, RES0.
Otherwise
TTA
28
28
0
Traps EL0 and EL1 System register accesses to all implemented trace System registers from both Execution states to EL1, or to EL2 when it is implemented and enabled in the current Security state and HCR_EL2.TGE is 1, as follows:
In AArch64 state, accesses to trace System registers are trapped, reported using EC syndrome value 0x18.
In AArch32 state, MRC and MCR accesses to trace System registers are trapped, reported using EC syndrome value 0x05.
In AArch32 state, MRRC and MCRR accesses to trace System registers are trapped, reported using EC syndrome value 0x0C.
The ETMv4 architecture and ETE do not permit EL0 to access the trace System registers. If the trace unit implements FEAT_ETMv4 or FEAT_ETE, EL0 accesses to the trace System registers are UNDEFINED, and any resulting exception is higher priority than an exception that would be generated because the value of CPACR_EL1.TTA is 1.The Arm architecture does not provide traps on trace register accesses through the optional memory-mapped interface.
System register accesses to the trace System registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this field has no effect on execution at EL0.
0b0
This control does not cause any instructions to be trapped.
0b1
This control causes EL0 and EL1 System register accesses to all implemented trace System registers to be trapped.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
CPACRMASK_EL1.TTA == '1'
RO
When System register access to the trace unit registers is implemented
28
28
28
Reserved, RES0.
Otherwise
27
26
27:26
Reserved, RES0.
SMEN
25
24
1:0
Traps execution at EL1 and EL0 of SME instructions, SVE instructions when FEAT_SVE is not implemented or the PE is in Streaming SVE mode, and instructions that directly access the SVCR or SMCR_EL1 System registers to EL1, or to EL2 when EL2 is implemented and enabled in the current Security state and HCR_EL2.TGE is 1.
When instructions that directly access the SVCR System register are trapped with reference to this control, the MSR SVCRSM, MSR SVCRZA, and MSR SVCRSMZA instructions are also trapped.
The exception is reported using EC syndrome value 0x1D, with an ISS code of 0x0000000.
This field does not affect whether Streaming SVE or SME register values are valid.
A trap taken as a result of CPACR_EL1.SMEN has precedence over a trap taken as a result of CPACR_EL1.FPEN.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this field has no effect on execution at EL0.
0b00
This control causes execution of these instructions at EL1 and EL0 to be trapped.
0b01
This control causes execution of these instructions at EL0 to be trapped, but does not cause execution of any instructions at EL1 to be trapped.
0b10
This control causes execution of these instructions at EL1 and EL0 to be trapped.
0b11
This control does not cause execution of any instructions to be trapped.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
CPACRMASK_EL1.SMEN == '1'
RO
When FEAT_SME is implemented
25
24
25:24
Reserved, RES0.
Otherwise
23
22
23:22
Reserved, RES0.
FPEN
21
20
21:20
Traps execution at EL1 and EL0 of instructions that access the Advanced SIMD and floating-point registers from both Execution states to EL1, reported using EC syndrome value 0x07, or to EL2 reported using EC syndrome value 0x00 when EL2 is implemented and enabled in the current Security state and HCR_EL2.TGE is 1, as follows:
In AArch64 state, accesses to
FPMR,
FPCR, FPSR, and any of the SIMD and floating-point registers V0-V31, including their views as D0-D31 registers or S0-31 registers.
In AArch32 state, FPSCR, and any of the SIMD and floating-point registers Q0-15, including their views as D0-D31 registers or S0-31 registers.
Traps execution at EL1 and EL0 of
SME and
SVE instructions
to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1.
The exception is reported using EC syndrome value 0x07.
A trap taken as a result of CPACR_EL1.SMEN has precedence over a trap taken as a result of CPACR_EL1.FPEN.
A trap taken as a result of CPACR_EL1.ZEN has precedence over a trap taken as a result of CPACR_EL1.FPEN.
Writes to MVFR0, MVFR1, and MVFR2 from EL1 or higher are CONSTRAINED UNPREDICTABLE and whether these accesses can be trapped by this control depends on implemented CONSTRAINED UNPREDICTABLE behavior.
Attempts to write to the FPSID count as use of the registers for accesses from EL1 or higher.Accesses from EL0 to FPSID, MVFR0, MVFR1, MVFR2, and FPEXC are UNDEFINED, and any resulting exception is higher priority than an exception that would be generated because the value of CPACR_EL1.FPEN is not 0b11.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this field has no effect on execution at EL0.
0b00
This control causes execution of these instructions at EL1 and EL0 to be trapped.
0b01
This control causes execution of these instructions at EL0 to be trapped, but does not cause execution of any instructions at EL1 to be trapped.
0b10
This control causes execution of these instructions at EL1 and EL0 to be trapped.
0b11
This control does not cause execution of any instructions to be trapped.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
CPACRMASK_EL1.FPEN == '1'
RO
19
18
19:18
Reserved, RES0.
ZEN
17
16
1:0
Traps execution at EL1 and EL0 of SVE instructions when the PE is not in Streaming SVE mode, and instructions that directly access the ZCR_EL1 System register to EL1, or to EL2 when EL2 is implemented and enabled in the current Security state and HCR_EL2.TGE is 1.
The exception is reported using EC syndrome value 0x19.
A trap taken as a result of CPACR_EL1.ZEN has precedence over a trap taken as a result of CPACR_EL1.FPEN.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this field has no effect on execution at EL0.
0b00
This control causes execution of these instructions at EL1 and EL0 to be trapped.
0b01
This control causes execution of these instructions at EL0 to be trapped, but does not cause execution of any instructions at EL1 to be trapped.
0b10
This control causes execution of these instructions at EL1 and EL0 to be trapped.
0b11
This control does not cause execution of any instructions to be trapped.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
CPACRMASK_EL1.ZEN == '1'
RO
When FEAT_SVE is implemented
17
16
17:16
Reserved, RES0.
Otherwise
15
0
15:0
Reserved, RES0.
When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name CPACR_EL1 or CPACR_EL12 are not guaranteed to be ordered with respect to accesses using the other accessor name.
If FEAT_SRMASK is implemented, accesses to CPACR_EL1 are masked by CPACRMASK_EL1.
MRS <Xt>, CPACR_EL1
if !IsFeatureImplemented(FEAT_AA64) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TCPAC == '1' then
Undefined();
elsif EL2Enabled() && CPTR_EL2().TCPAC == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().CPACR_EL1 == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3().TCPAC == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
elsif EffectiveHCR_EL2_NVx() IN {'111'} then
X{64}(t) = NVMem(0x100);
else
X{64}(t) = CPACR_EL1();
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TCPAC == '1' then
Undefined();
elsif HaveEL(EL3) && CPTR_EL3().TCPAC == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
elsif ELIsInHost(EL2) then
X{64}(t) = CPTR_EL2();
else
X{64}(t) = CPACR_EL1();
end;
elsif PSTATE.EL == EL3 then
X{64}(t) = CPACR_EL1();
end;
MSR CPACR_EL1, <Xt>
if !IsFeatureImplemented(FEAT_AA64) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TCPAC == '1' then
Undefined();
elsif EL2Enabled() && CPTR_EL2().TCPAC == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().CPACR_EL1 == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3().TCPAC == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
elsif EffectiveHCR_EL2_NVx() IN {'111'} then
NVMem(0x100) = X{64}(t);
else
CPACR_EL1() = X{64}(t);
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TCPAC == '1' then
Undefined();
elsif HaveEL(EL3) && CPTR_EL3().TCPAC == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
elsif ELIsInHost(EL2) then
CPTR_EL2() = X{64}(t);
else
CPACR_EL1() = X{64}(t);
end;
elsif PSTATE.EL == EL3 then
CPACR_EL1() = X{64}(t);
end;
MRS <Xt>, CPACR_EL12
When FEAT_VHE is implemented
if !IsFeatureImplemented(FEAT_AA64) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EffectiveHCR_EL2_NVx() == '101' then
X{64}(t) = NVMem(0x100);
elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then
AArch64_SystemAccessTrap(EL2, 0x18);
else
Undefined();
end;
elsif PSTATE.EL == EL2 then
if ELIsInHost(EL2) then
if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TCPAC == '1' then
Undefined();
elsif HaveEL(EL3) && CPTR_EL3().TCPAC == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
else
X{64}(t) = CPACR_EL1();
end;
else
Undefined();
end;
elsif PSTATE.EL == EL3 then
if ELIsInHost(EL2) then
X{64}(t) = CPACR_EL1();
else
Undefined();
end;
end;
MSR CPACR_EL12, <Xt>
When FEAT_VHE is implemented
if !IsFeatureImplemented(FEAT_AA64) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EffectiveHCR_EL2_NVx() == '101' then
NVMem(0x100) = X{64}(t);
elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then
AArch64_SystemAccessTrap(EL2, 0x18);
else
Undefined();
end;
elsif PSTATE.EL == EL2 then
if ELIsInHost(EL2) then
if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TCPAC == '1' then
Undefined();
elsif HaveEL(EL3) && CPTR_EL3().TCPAC == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
else
CPACR_EL1() = X{64}(t);
end;
else
Undefined();
end;
elsif PSTATE.EL == EL3 then
if ELIsInHost(EL2) then
CPACR_EL1() = X{64}(t);
else
Undefined();
end;
end;
MRS <Xt>, CPACRALIAS_EL1
When FEAT_SRMASK is implemented
if !IsFeatureImplemented(FEAT_AA64) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TCPAC == '1' then
Undefined();
elsif EL2Enabled() && CPTR_EL2().TCPAC == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGRTR2_EL2().nCPACRALIAS_EL1 == '0') then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3().TCPAC == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
elsif EffectiveHCR_EL2_NVx() IN {'111'} then
X{64}(t) = NVMem(0x100);
else
X{64}(t) = CPACR_EL1();
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TCPAC == '1' then
Undefined();
elsif HaveEL(EL3) && CPTR_EL3().TCPAC == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
elsif ELIsInHost(EL2) then
X{64}(t) = CPTR_EL2();
else
X{64}(t) = CPACR_EL1();
end;
elsif PSTATE.EL == EL3 then
X{64}(t) = CPACR_EL1();
end;
MSR CPACRALIAS_EL1, <Xt>
When FEAT_SRMASK is implemented
if !IsFeatureImplemented(FEAT_AA64) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TCPAC == '1' then
Undefined();
elsif EL2Enabled() && CPTR_EL2().TCPAC == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGWTR2_EL2().nCPACRALIAS_EL1 == '0') then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3().TCPAC == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
elsif EffectiveHCR_EL2_NVx() IN {'111'} then
NVMem(0x100) = X{64}(t);
else
CPACR_EL1() = X{64}(t);
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TCPAC == '1' then
Undefined();
elsif HaveEL(EL3) && CPTR_EL3().TCPAC == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
elsif ELIsInHost(EL2) then
CPTR_EL2() = X{64}(t);
else
CPACR_EL1() = X{64}(t);
end;
elsif PSTATE.EL == EL3 then
CPACR_EL1() = X{64}(t);
end;
2026-03-26 20:27:25
2026-03_rel