CPTR_EL2 Architectural Feature Trap Register (EL2) when FEAT_AA64 is implemented HCPTR Architectural AArch32 31 0 31 0 31 0 31 0 Controls trapping to EL2 of accesses to CPACR, CPACR_EL1, trace, Activity Monitor, SME, Streaming SVE, SVE, and Advanced SIMD and floating-point functionality. Virt If EL2 is not implemented, this register is RES0 from EL3. This register has no effect if EL2 is not enabled in the current Security state. CPTR_EL2 is a 64-bit register. When EffectiveHCR_EL2_E2H() == '1' EffectiveHCR_EL2_E2H() == '1' 63 32 63:32 Reserved, RES0. TCPAC 31 31 31 In AArch64 state, traps accesses to CPACR_EL1 from EL1 to EL2, when EL2 is enabled in the current Security state. The exception is reported using EC syndrome value 0x18. In AArch32 state, traps accesses to CPACR from EL1 to EL2, when EL2 is enabled in the current Security state. The exception is reported using EC syndrome value 0x03. When the Effective value of HCR_EL2.TGE is 1, this control does not cause any instructions to be trapped. CPACR_EL1 and CPACR are not accessible at EL0. 0b0 This control does not cause any instructions to be trapped. 0b1 EL1 accesses to CPACR_EL1 and CPACR are trapped to EL2, when EL2 is enabled in the current Security state. AU FEAT_SRMASK is implemented EL2 is the current Exception level IsSystemRegisterMaskingEnabled(EL2) CPTRMASK_EL2.TCPAC == '1' RO TAM 30 30 0 Trap Activity Monitor access. Traps EL1 and EL0 accesses to all Activity Monitors System registers to EL2, as follows: In AArch64 state, accesses to the following registers are trapped to EL2, reported using EC syndrome value 0x18: AMUSERENR_EL0, AMCFGR_EL0, AMCGCR_EL0, AMCNTENCLR0_EL0, AMCNTENCLR1_EL0, AMCNTENSET0_EL0, AMCNTENSET1_EL0, AMCR_EL0, AMEVCNTR0<n>_EL0, AMEVCNTR1<n>_EL0, AMEVTYPER0<n>_EL0, and AMEVTYPER1<n>_EL0. In AArch32 state, MRC or MCR accesses to the following registers are trapped to EL2 and reported using EC syndrome value 0x03: AMUSERENR, AMCFGR, AMCGCR, AMCNTENCLR0, AMCNTENCLR1, AMCNTENSET0, AMCNTENSET1, AMCR, AMEVTYPER0<n>, and AMEVTYPER1<n>. In AArch32 state, MRRC or MCRR accesses to AMEVCNTR0<n> and AMEVCNTR1<n>, are trapped to EL2, reported using EC syndrome value 0x04. 0b0 Accesses from EL1 and EL0 to Activity Monitors System registers are not trapped. 0b1 Accesses from EL1 and EL0 to Activity Monitors System registers are trapped to EL2, when EL2 is enabled in the current Security state. AU FEAT_SRMASK is implemented EL2 is the current Exception level IsSystemRegisterMaskingEnabled(EL2) CPTRMASK_EL2.TAM == '1' RO When FEAT_AMUv1 is implemented 30 30 30 Reserved, RES0. Otherwise E0POE 29 29 0 Enable access to POR_EL0. Traps EL0 accesses to POR_EL0 to EL2, from AArch64 state only. The exception is reported using EC syndrome value 0x18. 0b0 This control causes EL0 access to POR_EL0 to be trapped. 0b1 This control does not cause any instructions to be trapped. AU FEAT_SRMASK is implemented EL2 is the current Exception level IsSystemRegisterMaskingEnabled(EL2) CPTRMASK_EL2.E0POE == '1' RO When FEAT_S1POE is implemented 29 29 29 Reserved, RES0. Otherwise TTA 28 28 0 Traps System register accesses to all implemented trace System registers from both Execution states to EL2, when EL2 is enabled in the current Security state, as follows: In AArch64 state, accesses to trace System registers with op0=2, op1=1, and CRn<0b1000 are trapped to EL2, reported using EC syndrome value 0x18. In AArch32 state, MRC or MCR accesses to trace System registers with cpnum=14, opc1=1, and CRn<0b1000 are trapped to EL2, reported using EC syndrome value 0x05. The ETMv4 architecture and ETE do not permit EL0 to access the trace System registers. If the trace unit implements FEAT_ETMv4 or ETE, EL0 accesses to the trace System registers are UNDEFINED, and any resulting exception is higher priority than an exception that would be generated because the value of CPTR_EL2.TTA is 1. EL2 does not provide traps on trace register accesses through the optional Memory-mapped interface. System register accesses to the trace System registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken. 0b0 This control does not cause any instructions to be trapped. 0b1 Any attempt at EL0, EL1 or EL2, to execute a System register access to an implemented trace System register is trapped to EL2, when EL2 is enabled in the current Security state, unless HCR_EL2.TGE is 0 and it is trapped by CPACR.NSTRCDIS or CPACR_EL1.TTA. When HCR_EL2.TGE is 1, any attempt at EL0 or EL2 to execute a System register access to an implemented trace System register is trapped to EL2, when EL2 is enabled in the current Security state. AU FEAT_SRMASK is implemented EL2 is the current Exception level IsSystemRegisterMaskingEnabled(EL2) CPTRMASK_EL2.TTA == '1' RO When System register access to the trace unit registers is implemented 28 28 28 Reserved, RES0. Otherwise 27 26 27:26 Reserved, RES0. SMEN 25 24 1:0 Traps execution at EL2, EL1, and EL0 of SME instructions, SVE instructions when FEAT_SVE is not implemented or the PE is in Streaming SVE mode, and instructions that directly access the SVCR, SMCR_EL1, or SMCR_EL2 System registers to EL2, when EL2 is enabled in the current Security state. When instructions that directly access the SVCR System register are trapped with reference to this control, the MSR SVCRSM, MSR SVCRZA, and MSR SVCRSMZA instructions are also trapped. The exception is reported using EC syndrome value 0x1D, with an ISS code of 0x0000000. This field does not affect whether Streaming SVE or SME register values are valid. A trap taken as a result of CPTR_EL2.SMEN has precedence over a trap taken as a result of CPTR_EL2.FPEN. 0b00 This control causes execution of these instructions at EL2, EL1, and EL0 to be trapped. 0b01 When HCR_EL2.TGE is 0, this control does not cause execution of any instructions to be trapped. When HCR_EL2.TGE is 1, this control causes execution of these instructions at EL0 to be trapped, but does not cause execution of any instructions at EL2 to be trapped. 0b10 This control causes execution of these instructions at EL2, EL1, and EL0 to be trapped. 0b11 This control does not cause execution of any instructions to be trapped. AU FEAT_SRMASK is implemented EL2 is the current Exception level IsSystemRegisterMaskingEnabled(EL2) CPTRMASK_EL2.SMEN == '1' RO When FEAT_SME is implemented 25 24 25:24 Reserved, RES0. Otherwise 23 22 23:22 Reserved, RES0. FPEN 21 20 21:20 Traps execution at EL2, EL1, and EL0 of instructions that access the Advanced SIMD and floating-point registers from both Execution states to EL2, when EL2 is enabled in the current Security state. The exception is reported using EC syndrome value 0x07. Traps execution at EL2, EL1, and EL0 of SME and SVE instructions to EL2, when EL2 is enabled in the current Security state. The exception is reported using EC syndrome value 0x07. When FEAT_FPMR is implemented, traps execution at EL2, EL1, and EL0 of instructions that access FPMR to EL2, when EL2 is enabled in the current Security state. The exception is reported using EC syndrome value 0x07 A trap taken as a result of CPTR_EL2.SMEN has precedence over a trap taken as a result of CPTR_EL2.FPEN. A trap taken as a result of CPTR_EL2.ZEN has precedence over a trap taken as a result of CPTR_EL2.FPEN. Writes to MVFR0, MVFR1, and MVFR2 from EL1 or higher are CONSTRAINED UNPREDICTABLE and whether these accesses can be trapped by this control depends on implemented CONSTRAINED UNPREDICTABLE behavior. Attempts to write to the FPSID count as use of the registers for accesses from EL1 or higher.Accesses from EL0 to FPSID, MVFR0, MVFR1, MVFR2, and FPEXC are UNDEFINED, and any resulting exception is higher priority than an exception that would be generated because the value of CPTR_EL2.FPEN is not 0b11. 0b00 This control causes execution of these instructions at EL2, EL1, and EL0 to be trapped. 0b01 When HCR_EL2.TGE is 0, this control does not cause execution of any instructions to be trapped. When HCR_EL2.TGE is 1, this control causes execution of these instructions at EL0 to be trapped, but does not cause execution of any instructions at EL2 to be trapped. 0b10 This control causes execution of these instructions at EL2, EL1, and EL0 to be trapped. 0b11 This control does not cause execution of any instructions to be trapped. AU FEAT_SRMASK is implemented EL2 is the current Exception level IsSystemRegisterMaskingEnabled(EL2) CPTRMASK_EL2.FPEN == '1' RO 19 18 19:18 Reserved, RES0. ZEN 17 16 1:0 Traps execution at EL2, EL1, and EL0 of SVE instructions when the PE is not in Streaming SVE mode, and instructions that directly access the ZCR_EL1 or ZCR_EL2 System registers to EL2, when EL2 is enabled in the current Security state. The exception is reported using EC syndrome value 0x19. A trap taken as a result of CPTR_EL2.ZEN has precedence over a trap taken as a result of CPTR_EL2.FPEN. 0b00 This control causes execution of these instructions at EL2, EL1, and EL0 to be trapped. 0b01 When HCR_EL2.TGE is 0, this control does not cause execution of any instructions to be trapped. When HCR_EL2.TGE is 1, this control causes execution of these instructions at EL0 to be trapped, but does not cause execution of any instructions at EL2 to be trapped. 0b10 This control causes execution of these instructions at EL2, EL1, and EL0 to be trapped. 0b11 This control does not cause execution of any instructions to be trapped. AU FEAT_SRMASK is implemented EL2 is the current Exception level IsSystemRegisterMaskingEnabled(EL2) CPTRMASK_EL2.ZEN == '1' RO When FEAT_SVE is implemented 17 16 17:16 Reserved, RES0. Otherwise 15 0 15:0 Reserved, RES0. EffectiveHCR_EL2_E2H() == '0' This format applies in all Armv8.0 implementations. 63 32 63:32 Reserved, RES0. TCPAC 31 31 31 In AArch64 state, traps accesses to CPACR_EL1 from EL1 to EL2, when EL2 is enabled in the current Security state. The exception is reported using EC syndrome value 0x18. In AArch32 state, traps accesses to CPACR from EL1 to EL2, when EL2 is enabled in the current Security state. The exception is reported using EC syndrome value 0x03. When HCR_EL2.TGE is 1, this control does not cause any instructions to be trapped. CPACR_EL1 and CPACR are not accessible at EL0. 0b0 This control does not cause any instructions to be trapped. 0b1 EL1 accesses to the following registers are trapped to EL2, when EL2 is enabled in the current Security state: CPACR_EL1. CPACR. AU TAM 30 30 0 Trap Activity Monitor access. Traps EL1 and EL0 accesses to all Activity Monitors System registers to EL2, as follows: In AArch64 state, accesses to the following registers are trapped to EL2, reported using EC syndrome value 0x18: AMUSERENR_EL0, AMCFGR_EL0, AMCGCR_EL0, AMCNTENCLR0_EL0, AMCNTENCLR1_EL0, AMCNTENSET0_EL0, AMCNTENSET1_EL0, AMCR_EL0, AMEVCNTR0<n>_EL0, AMEVCNTR1<n>_EL0, AMEVTYPER0<n>_EL0, and AMEVTYPER1<n>_EL0. In AArch32 state, MCR or MRC accesses to the following registers are trapped to EL2 and reported using EC syndrome value 0x03: AMUSERENR, AMCFGR, AMCGCR, AMCNTENCLR0, AMCNTENCLR1, AMCNTENSET0, AMCNTENSET1, AMCR, AMEVTYPER0<n>, and AMEVTYPER1<n>. In AArch32 state, MCRR or MRRC accesses to AMEVCNTR0<n> and AMEVCNTR1<n>, are trapped to EL2, reported using EC syndrome value 0x04. 0b0 Accesses from EL1 and EL0 to Activity Monitors System registers are not trapped. 0b1 Accesses from EL1 and EL0 to Activity Monitors System registers are trapped to EL2, when EL2 is enabled in the current Security state. AU When FEAT_AMUv1 is implemented 30 30 30 Reserved, RES0. Otherwise 29 21 29:21 Reserved, RES0. TTA 20 20 0 Traps System register accesses to all implemented trace System registers from both Execution states to EL2, when EL2 is enabled in the current Security state, as follows: In AArch64 state, accesses to trace System registers with op0=2, op1=1, and CRn<0b1000 are trapped to EL2, reported using EC syndrome value 0x18. In AArch32 state, MRC or MCR accesses to trace System registers with cpnum=14, opc1=1, and CRn<0b1000 are trapped to EL2, reported using EC syndrome value 0x05. FEAT_ETMv4 and FEAT_ETE do not permit EL0 to access the trace System registers. EL0 accesses to the trace System registers are UNDEFINED, and any resulting exception is higher priority than an exception that would be generated because the value of CPTR_EL2.TTA is 1. EL2 does not provide traps on trace register accesses through the optional memory-mapped interface. System register accesses to the trace System registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken. 0b0 This control does not cause any instructions to be trapped. 0b1 Any attempt at EL0, EL1, or EL2, to execute a System register access to an implemented trace System register is trapped to EL2, when EL2 is enabled in the current Security state, unless it is trapped by one of the following controls: CPACR_EL1.TTA. CPACR.TRCDIS. AU When System register access to the trace unit registers is implemented 20 20 20 Reserved, RES0. Otherwise 19 14 19:14 Reserved, RES0. 13 13 13 Reserved, RES1. TSM 12 12 0 Traps execution at EL2, EL1, and EL0 of SME instructions, SVE instructions when FEAT_SVE is not implemented or the PE is in Streaming SVE mode, and instructions that directly access the SVCR, SMCR_EL1, or SMCR_EL2 System registers to EL2, when EL2 is enabled in the current Security state. When instructions that directly access the SVCR System register are trapped with reference to this control, the MSR SVCRSM, MSR SVCRZA, and MSR SVCRSMZA instructions are also trapped. The exception is reported using EC syndrome value 0x1D, with an ISS code of 0x0000000. This field does not affect whether Streaming SVE or SME register values are valid. A trap taken as a result of CPTR_EL2.TSM has precedence over a trap taken as a result of CPTR_EL2.TFP. 0b0 This control does not cause execution of any instructions to be trapped. 0b1 This control causes execution of these instructions at EL2, EL1, and EL0 to be trapped. AU When FEAT_SME is implemented 12 12 12 Reserved, RES1. Otherwise 11 11 11 Reserved, RES0. TFP 10 10 10 Traps execution of instructions which access the Advanced SIMD and floating-point functionality, from both Execution states to EL2, when EL2 is enabled in the current Security state, as follows: In AArch64 state, accesses to the following registers are trapped to EL2, reported using EC syndrome value 0x07: FPCR, FPSR, FPEXC32_EL2, and any of the SIMD and floating-point registers V0-V31, including their views as D0-D31 registers or S0-31 registers. If FEAT_FPMR is implemented, FPMR. In AArch32 state, accesses to the following registers are trapped to EL2, reported using EC syndrome value 0x07: MVFR0, MVFR1, MVFR2, FPSCR, FPEXC, and any of the SIMD and floating-point registers Q0-15, including their views as D0-D31 registers or S0-31 registers. For the purposes of this trap, the architecture defines a VMSR access to FPSID from EL1 or higher as an access to a SIMD and floating-point register. Otherwise, permitted VMSR accesses to FPSID are ignored. Traps execution at the same Exception levels of SME and SVE instructions to EL2, when EL2 is enabled in the current Security state. The exception is reported using EC syndrome value 0x07. A trap taken as a result of CPTR_EL2.TSM has precedence over a trap taken as a result of CPTR_EL2.TFP. A trap taken as a result of CPTR_EL2.TZ has precedence over a trap taken as a result of CPTR_EL2.TFP. FPEXC32_EL2 is not accessible from EL0 using AArch64. FPSID, MVFR0, MVFR1, and FPEXC are not accessible from EL0 using AArch32. 0b0 This control does not cause execution of any instructions to be trapped. 0b1 This control causes execution of these instructions at EL2, EL1, and EL0 to be trapped. AU 9 9 9 Reserved, RES1. TZ 8 8 0 Traps execution at EL2, EL1, and EL0 of SVE instructions when the PE is not in Streaming SVE mode, and instructions that directly access the ZCR_EL2 or ZCR_EL1 System registers to EL2, when EL2 is enabled in the current Security state. The exception is reported using EC syndrome value 0x19. A trap taken as a result of CPTR_EL2.TZ has precedence over a trap taken as a result of CPTR_EL2.TFP. 0b0 This control does not cause execution of any instructions to be trapped. 0b1 This control causes execution of these instructions at EL2, EL1, and EL0 to be trapped. AU When FEAT_SVE is implemented 8 8 8 Reserved, RES1. Otherwise 7 0 7:0 Reserved, RES1. When EffectiveHCR_EL2_E2H() == '1' When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the accessor name CPTR_EL2 or CPACR_EL1 are not guaranteed to be ordered with respect to accesses using the other accessor name. If FEAT_SRMASK is implemented, accesses to CPTR_EL2 are masked by CPTRMASK_EL2. MRS <Xt>, CPTR_EL2 if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TCPAC == '1' then Undefined(); elsif HaveEL(EL3) && CPTR_EL3().TCPAC == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = CPTR_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = CPTR_EL2(); end; MSR CPTR_EL2, <Xt> if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TCPAC == '1' then Undefined(); elsif HaveEL(EL3) && CPTR_EL3().TCPAC == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else CPTR_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then CPTR_EL2() = X{64}(t); end; MRS <Xt>, CPACR_EL1 When FEAT_VHE is implemented if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TCPAC == '1' then Undefined(); elsif EL2Enabled() && CPTR_EL2().TCPAC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().CPACR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TCPAC == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x100); else X{64}(t) = CPACR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TCPAC == '1' then Undefined(); elsif HaveEL(EL3) && CPTR_EL3().TCPAC == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = CPTR_EL2(); else X{64}(t) = CPACR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = CPACR_EL1(); end; MSR CPACR_EL1, <Xt> When FEAT_VHE is implemented if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TCPAC == '1' then Undefined(); elsif EL2Enabled() && CPTR_EL2().TCPAC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().CPACR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TCPAC == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x100) = X{64}(t); else CPACR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TCPAC == '1' then Undefined(); elsif HaveEL(EL3) && CPTR_EL3().TCPAC == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then CPTR_EL2() = X{64}(t); else CPACR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then CPACR_EL1() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel