CPTRMASK_EL2 Architectural Feature Trap Masking Register when FEAT_SRMASK is implemented and FEAT_AA64 is implemented Mask register to prevent updates of fields in CPTR_EL2 on writes. Other If EL2 is not implemented, this register is RES0 from EL3. This register has no effect if EL2 is not enabled in the current Security state. CPTRMASK_EL2 is a 64-bit register. 63 32 63:32 Reserved, RES0. TCPAC 31 31 31 Mask bit for TCPAC. 0b0 CPTR_EL2.TCPAC is writable. 0b1 CPTR_EL2.TCPAC is not writable. '0' AU TAM 30 30 0 Mask bit for TAM. 0b0 CPTR_EL2.TAM is writable. 0b1 CPTR_EL2.TAM is not writable. '0' AU When FEAT_AMUv1 is implemented 30 30 30 Reserved, RES0. Otherwise E0POE 29 29 0 Mask bit for E0POE. 0b0 CPTR_EL2.E0POE is writable. 0b1 CPTR_EL2.E0POE is not writable. '0' AU When FEAT_S1POE is implemented 29 29 29 Reserved, RES0. Otherwise TTA 28 28 0 Mask bit for TTA. 0b0 CPTR_EL2.TTA is writable. 0b1 CPTR_EL2.TTA is not writable. '0' AU When System register access to the trace unit registers is implemented 28 28 28 Reserved, RES0. Otherwise 27 25 27:25 Reserved, RES0. SMEN 24 24 0 Mask bit for SMEN. 0b0 CPTR_EL2.SMEN is writable. 0b1 CPTR_EL2.SMEN is not writable. '0' AU When FEAT_SME is implemented 24 24 24 Reserved, RES0. Otherwise 23 21 23:21 Reserved, RES0. FPEN 20 20 20 Mask bit for FPEN. 0b0 CPTR_EL2.FPEN is writable. 0b1 CPTR_EL2.FPEN is not writable. '0' AU 19 17 19:17 Reserved, RES0. ZEN 16 16 0 Mask bit for ZEN. 0b0 CPTR_EL2.ZEN is writable. 0b1 CPTR_EL2.ZEN is not writable. '0' AU When FEAT_SVE is implemented 16 16 16 Reserved, RES0. Otherwise 15 0 15:0 Reserved, RES0. When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the accessor name CPTRMASK_EL2 or CPACRMASK_EL1 are not guaranteed to be ordered with respect to accesses using the other accessor name. MRS <Xt>, CPTRMASK_EL2 if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = CPTRMASK_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = CPTRMASK_EL2(); end; MSR CPTRMASK_EL2, <Xt> if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !IsZero(CPTRMASK_EL2()) then Undefined(); else CPTRMASK_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then CPTRMASK_EL2() = X{64}(t); end; MRS <Xt>, CPACRMASK_EL1 if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGRTR2_EL2().nCPACRMASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SRMASKEn == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x320); else X{64}(t) = CPACRMASK_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = CPTRMASK_EL2(); else X{64}(t) = CPACRMASK_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = CPACRMASK_EL1(); end; MSR CPACRMASK_EL1, <Xt> if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGWTR2_EL2().nCPACRMASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SRMASKEn == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x320) = X{64}(t); elsif !IsZero(CPACRMASK_EL1()) then Undefined(); else CPACRMASK_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then if !IsZero(CPTRMASK_EL2()) then Undefined(); else CPTRMASK_EL2() = X{64}(t); end; else CPACRMASK_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then CPACRMASK_EL1() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel